公开(公告)号：US07596651B2

公开(公告)日：2009-09-29

申请号：US11754821

申请日：2007-05-29

申请人： Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

发明人： Stephen L. Blinick ,  Carol Spanel ,  Andrew Dale Walls

IPC分类号： G06F9/06

CPC分类号： G06F13/385

摘要： One embodiment of an adapter card in accordance with the invention includes a circuit board connectable to a motherboard of a computer system. A logic chip is connected to the circuit board to provide functionality to the adapter card. One or more programmable devices are connected to the circuit board and store data read by the logic chip upon initialization. This data may include first character data to program the logic chip to have a first character and second character data to program the logic chip to have a second character. A switching mechanism is provided to switch between the first and second character data in response to an external input, thereby causing the logic chip to read one of the first and second character data.

摘要翻译： 根据本发明的适配器卡的一个实施例包括可连接到计算机系统的主板的电路板。 逻辑芯片连接到电路板以向适配器卡提供功能。 一个或多个可编程设备连接到电路板，并在初始化时存储由逻辑芯片读取的数据。 该数据可以包括用于对逻辑芯片编程以具有第一字符和第二字符数据的第一字符数据，以将逻辑芯片编程为具有第二字符。 提供切换机制以响应于外部输入在第一和第二字符数据之间切换，从而使逻辑芯片读取第一和第二字符数据之一。

公开(公告)号：US20080263255A1

公开(公告)日：2008-10-23

申请号：US11738142

申请日：2007-04-20

申请人： Stephen L. Blinick ,  Cheng-Chung Song ,  Carol Spanel ,  Andrew Dale Walls

发明人： Stephen L. Blinick ,  Cheng-Chung Song ,  Carol Spanel ,  Andrew Dale Walls

IPC分类号： G06F13/36

CPC分类号： G06F11/2038 ,  G06F11/2033 ,  G06F11/2046

摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

公开(公告)号：US09075720B2

公开(公告)日：2015-07-07

申请号：US12897555

申请日：2010-10-04

申请人： Stephen L. Blinick ,  Charles S. Cardinell ,  Roger G. Hathorn ,  Bernhard Laubli ,  Miguel A. Montoya ,  Timothy J. Van Patten

发明人： Stephen L. Blinick ,  Charles S. Cardinell ,  Roger G. Hathorn ,  Bernhard Laubli ,  Miguel A. Montoya ,  Timothy J. Van Patten

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0879 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0833 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/127 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/303 ,  G06F2212/604 ,  G06F2212/62 ,  G06F2212/657

摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

摘要翻译： 提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。 在目标地址的缓存中分配高速缓存行。 为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。 数据被写入缓存行。 响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

公开(公告)号：US08407710B2

公开(公告)日：2013-03-26

申请号：US12904715

申请日：2010-10-14

申请人： Stephen L. Blinick ,  Steven E. Klein ,  Daniel W. Sherman

发明人： Stephen L. Blinick ,  Steven E. Klein ,  Daniel W. Sherman

IPC分类号： G06F9/46 ,  G06F3/00 ,  G06F5/00 ,  G06F12/00 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F9/4843

摘要： Systems and methods for scanning ports for work are provided. One system includes one or more processors, multiple ports, a first tracking mechanism, and a second tracking mechanism for tracking high priority work and low priority work, respectively. The processor(s) is/are configured to perform the below method. One method includes scanning the ports, finding high priority work on a port, and accepting or declining the high priority work. The method further includes changing a designation of the processor to TRUE in the first tracking mechanism if the processor accepts the high priority work such that the processor is allowed to perform the high priority work on the port. Also provided are computer storage mediums including computer code for performing the above method.

摘要翻译： 提供扫描工作端口的系统和方法。 一个系统包括分别用于跟踪高优先级工作和低优先级工作的一个或多个处理器，多个端口，第一跟踪机构和第二跟踪机构。 处理器被配置为执行以下方法。 一种方法包括扫描端口，在端口上找到高优先级的工作，以及接受或拒绝高优先级的工作。 该方法还包括如果处理器接受高优先级的工作，使处理器能够在端口上执行高优先级的工作，则在第一跟踪机构中将处理器的指定改变为TRUE。 还提供了包括用于执行上述方法的计算机代码的计算机存储介质。

公开(公告)号：US20120084514A1

公开(公告)日：2012-04-05

申请号：US12897555

申请日：2010-10-04

申请人： Stephen L. Blinick ,  Charles S. Cardinell ,  Roger G. Hathorn ,  Bernhard Laubli ,  Miguel A. Montoya ,  Timothy J. Van Patten

发明人： Stephen L. Blinick ,  Charles S. Cardinell ,  Roger G. Hathorn ,  Bernhard Laubli ,  Miguel A. Montoya ,  Timothy J. Van Patten

IPC分类号： G06F12/08 ,  G06F13/24 ,  G06F12/00

CPC分类号： G06F12/0879 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0833 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/127 ,  G06F12/1475 ,  G06F2212/1052 ,  G06F2212/303 ,  G06F2212/604 ,  G06F2212/62 ,  G06F2212/657

摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.

摘要翻译： 提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。 在目标地址的缓存中分配高速缓存行。 为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。 数据被写入缓存行。 响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。

公开(公告)号：US07870417B2

公开(公告)日：2011-01-11

申请号：US11738142

申请日：2007-04-20

申请人： Stephen L. Blinick ,  Cheng-Chung Song ,  Carol Spanel ,  Andrew Dale Walls

发明人： Stephen L. Blinick ,  Cheng-Chung Song ,  Carol Spanel ,  Andrew Dale Walls

IPC分类号： G06F11/00

CPC分类号： G06F11/2038 ,  G06F11/2033 ,  G06F11/2046

摘要： An apparatus, system, and method are disclosed for adapter card failover. A switch module connects a first processor complex to an adapter card through a first port as an owner processor complex. The owner processor complex manages the adapter card except for a second port and receives error messages from the adapter card. The switch module further connects a second processor complex to the adapter card through the second port as a non-owner processor complex. The non-owner processor complex manages the second port. A detection module detects a failure of the first processor complex. A setup module modifies the switch module to logically connect the second processor complex to the adapter card as the owner processor complex and to logically disconnect the first processor complex from the adapter card in response to detecting the failure.

摘要翻译： 公开了用于适配器卡故障切换的装置，系统和方法。 开关模块通过作为所有者处理器的第一端口将第一处理器复合体连接到适配器卡。 所有者处理器复合体管理适配器卡，但第二个端口除外，并从适配器卡接收错误消息。 交换机模块通过第二端口进一步将第二处理器复合体连接到适配器卡，作为非所有者处理器复合体。 非所有者处理器复合体管理第二个端口。 检测模块检测第一处理器复杂的故障。 设置模块修改交换机模块以将所有者处理器复杂化，将第二处理器复合体逻辑连接到适配器卡，并根据检测到故障从逻辑上断开第一个处理器复合体与适配器卡的连接。

公开(公告)号：US20090006809A1

公开(公告)日：2009-01-01

申请号：US11769083

申请日：2007-06-27

申请人： Stephen L. Blinick ,  Chiahong Chen

发明人： Stephen L. Blinick ,  Chiahong Chen

IPC分类号： G06F15/76

CPC分类号： G06F9/44505 ,  G06F8/65 ,  G06F9/4401

摘要： Updating code of a single processor in a multi-processor system includes halting transactions processed by a first processor in the system and processing of transactions by a second processor in the system are maintained. The first processor then receives new code and an operating system running on the first processor is terminated whereby all processes and threads being executed by the first processor are terminated. Execution of a self-reset of the first processor is commenced and interrupts associated with the first processor are disabled. Only those system resources exclusively associated with the first processor are reset, and memory transactions associated with the first processor are disabled. An image of the new code is copied into memory associated with the first processor, registers associated with the first processor are reset and the new code is booted by the first processor.

摘要翻译： 在多处理器系统中更新单个处理器的代码包括停止由系统中的第一处理器处理的事务，并且维护由系统中的第二处理器处理事务的处理。 然后，第一处理器接收新的代码，并且终止在第一处理器上运行的操作系统，由此终止由第一处理器执行的所有进程和线程。 开始执行第一处理器的自复位，并且禁用与第一处理器相关联的中断。 只有与第一处理器完全相关联的系统资源被重置，并且与第一处理器相关联的存储器事务被禁用。 将新代码的图像复制到与第一处理器相关联的存储器中，与第一处理器相关联的寄存器被复位，并且新代码由第一处理器引导。

公开(公告)号：US07340595B2

公开(公告)日：2008-03-04

申请号：US11031605

申请日：2005-01-07

申请人： Stephen L. Blinick ,  Charles S. Cardinell ,  Ricardo S. Padilla

发明人： Stephen L. Blinick ,  Charles S. Cardinell ,  Ricardo S. Padilla

IPC分类号： G06F9/445 ,  G06F15/177

CPC分类号： G06F11/1417 ,  G06F11/1666 ,  G06F11/2284

摘要： A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image.

摘要翻译： 多个执行路径闪存系统包括主闪存映像，主要和辅助POST和引导可执行文件。 次级可执行文件与主要可执行文件偏移预定的偏移地址。 如果在引导期间遇到损坏的数据，则异常处理程序设置偏移位，导致预定的偏移地址被添加到当前指令地址。 如果在二级可执行文件中遇到损坏的数据，则偏移位被复位。 也可以使用可选的冗余闪光图像。 在主闪存映像的主要和次要可执行文件中的相同相对地址的故障将导致异常处理程序将控制传输到冗余闪存映像。 冗余闪存映像的主要和次要可执行文件中的相同相对地址的后续故障将导致冗余异常处理程序将控制权传输回主Flash映像。