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公开(公告)号：US09075720B2
公开(公告)日：2015-07-07
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译： 提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。 在目标地址的缓存中分配高速缓存行。 为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。 数据被写入缓存行。 响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。
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2.发明申请SELECTING DIRECT MEMORY ACCESS ENGINES IN AN ADAPTOR FOR PROCESSING INPUT/OUTPUT (I/O) REQUESTS RECEIVED AT THE ADAPTOR 有权在适配器中选择直接存储器访问引擎，用于处理在适配器中接收的输入/输出（I / O）请求公开(公告)号：US20120303842A1
公开(公告)日：2012-11-29
申请号：US13118093
申请日：2011-05-27
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F9/5011 , G06F9/505
摘要： Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.
摘要翻译： 提供了一种用于在适配器中选择直接存储器访问（DMA）引擎以用于处理在适配器处接收的输入/输出请求的计算机程序产品，系统和方法。 确定将多个处理器分配给DMA引擎，其中分配每个处理器以使用DMA引擎之一。 通过确定分配给处理器的处理I / O请求相关工作的DMA引擎并访问确定的DMA引擎来执行与I / O相关的工作来处理针对存储器的接收的I / O请求的I / O请求相关工作 。
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公开(公告)号：US20120084514A1
公开(公告)日：2012-04-05
申请号：US12897555
申请日：2010-10-04
申请人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
发明人： Stephen L. Blinick , Charles S. Cardinell , Roger G. Hathorn , Bernhard Laubli , Miguel A. Montoya , Timothy J. Van Patten
CPC分类号： G06F12/0879 , G06F12/0802 , G06F12/0804 , G06F12/0833 , G06F12/0891 , G06F12/1009 , G06F12/127 , G06F12/1475 , G06F2212/1052 , G06F2212/303 , G06F2212/604 , G06F2212/62 , G06F2212/657
摘要： Provided are a computer program product, system, and method for locking a cache line for a burst write operations on a bus. A cache line is allocated in a cache for a target address. A lock is set for the cache line, wherein setting the lock prevents the data in the cache line from being cast out. Data is written to the cache line. All the data in the cache line is flushed to the target address over a bus in response to completing writing to the cache line.
摘要翻译： 提供了一种用于在总线上锁定用于突发写入操作的高速缓存行的计算机程序产品，系统和方法。 在目标地址的缓存中分配高速缓存行。 为缓存行设置锁定，其中设置锁定防止高速缓存行中的数据被抛出。 数据被写入缓存行。 响应于完成对高速缓存线的写入，高速缓存行中的所有数据都通过总线刷新到目标地址。
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公开(公告)号：US08935511B2
公开(公告)日：2015-01-13
申请号：US12902047
申请日：2010-10-11
CPC分类号： G06F9/30087 , G06F1/12 , G06F1/14 , G06F11/1675
摘要： Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.
摘要翻译： 提供了一种用于确定处理器偏移以同步处理器时间值的计算机程序产品，系统和方法。 确定主处理器偏离主处理器的多个时间值之一和从属处理器之一的时间值的偏移。 确定从处理器偏移，其中从主处理器偏移确定每个从处理器偏移，主处理器的时间值之一和从属处理器的时间值之一。 主处理器的当前时间值由主处理器偏移量调整。 每个从属处理器的当前时间值由对其时间值正在调整的从属处理器的从属处理器偏移进行调整。
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公开(公告)号：US08850262B2
公开(公告)日：2014-09-30
申请号：US12902501
申请日：2010-10-12
CPC分类号： G06F11/0757 , G06F11/0724
摘要： An approach to detecting processor failure in a multi-processor environment is disclosed. The approach may include having each CPU in the system responsible for monitoring another CPU in the system. A CPUn reads a timestampn+1 created by CPUn+1 which CPUn is monitoring from a shared memory location. The CPUn reads its own timestampn and compares the two timestamps to calculate a delta value. If the delta value is above a threshold, the CPUn determines that CPUn+1 has failed and initiates error handling for the CPUs in the system. One CPU may be designated a master CPU, and be responsible for beginning the error handling process. In such embodiments, the CPUn may initiate error handling by notifying the master CPU that CPUn+1 has failed. If CPUn+1 is the master CPU, the CPUn may take additional steps to initiate error handling, and may broadcast a non-critical interrupt to all CPUs, triggering error handling.
摘要翻译： 公开了一种在多处理器环境中检测处理器故障的方法。 该方法可以包括使系统中的每个CPU负责监视系统中的另一个CPU。 CPUn读取CPUn + 1创建的时间戳+1，CPUn正在从共享内存位置进行监控。 CPUn读取自己的时间戳，并比较两个时间戳来计算增量值。 如果增量值高于阈值，CPUn确定CPUn + 1失败，并启动系统中CPU的错误处理。 一个CPU可能被指定为主CPU，并负责开始错误处理过程。 在这种实施例中，CPUn可以通过通知主CPU CPUn + 1失败来启动错误处理。 如果CPUn + 1是主CPU，CPUn可能会采取额外的步骤来启动错误处理，并可能会向所有CPU广播非关键中断，从而触发错误处理。
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公开(公告)号：US20120089815A1
公开(公告)日：2012-04-12
申请号：US12902047
申请日：2010-10-11
IPC分类号： G06F15/76
CPC分类号： G06F9/30087 , G06F1/12 , G06F1/14 , G06F11/1675
摘要： Provided are a computer program product, system, and method for determining processor offsets to synchronize processor time values. A determination is made of a master processor offset from one of a plurality of time values of the master processor and a time value of one of the slave processors. A determination is made of slave processor offsets, wherein each slave processor offset is determined from the master processor offset, one of the time values of the master processor, and a time value of the slave processor. A current time value of the master processor is adjusted by the master processor offset. A current time value of each of the slave processors is adjusted by the slave processor offset for the slave processor whose time value is being adjusted.
摘要翻译： 提供了一种用于确定处理器偏移以同步处理器时间值的计算机程序产品，系统和方法。 确定主处理器偏离主处理器的多个时间值之一和从属处理器之一的时间值的偏移。 确定从处理器偏移，其中从主处理器偏移确定每个从处理器偏移，主处理器的时间值之一和从属处理器的时间值之一。 主处理器的当前时间值由主处理器偏移量调整。 每个从属处理器的当前时间值由对其时间值正在调整的从属处理器的从属处理器偏移进行调整。
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7.发明授权Selecting direct memory access engines in an adaptor input/output (I/O) requests received at the adaptor 有权在适配器上接收的适配器输入/输出（I / O）请求中选择直接内存访问引擎公开(公告)号：US08904058B2
公开(公告)日：2014-12-02
申请号：US13118093
申请日：2011-05-27
CPC分类号： G06F13/28 , G06F9/5011 , G06F9/505
摘要： Provided are a computer program product, system, and method for selecting Direct Memory Access (DMA) engines in an adaptor for processing Input/Output requests received at the adaptor. A determination is made of an assignment of a plurality of processors to the DMA engines, wherein each processor is assigned to use one of the DMA engines. I/O request related work for a received I/O request directed to the storage is processed by determining the DMA engine assigned to the processor processing the I/O request related work and accessing the determined DMA engine to perform the I/O related work.
摘要翻译： 提供了一种用于在适配器中选择直接存储器访问（DMA）引擎以用于处理在适配器处接收的输入/输出请求的计算机程序产品，系统和方法。 确定将多个处理器分配给DMA引擎，其中分配每个处理器以使用DMA引擎之一。 通过确定分配给处理器的处理I / O请求相关工作的DMA引擎并访问确定的DMA引擎来执行与I / O相关的工作来处理针对存储器的接收的I / O请求的I / O请求相关工作 。
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公开(公告)号：US08904053B2
公开(公告)日：2014-12-02
申请号：US13470137
申请日：2012-05-11
CPC分类号： G06F13/366 , G06F3/06 , G06F3/061 , G06F3/0613 , G06F3/0635 , G06F3/0655 , G06F3/067 , G06F13/385
摘要： In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.
摘要翻译： 在本说明书的一个方面，在具有多个CPU和多个I / O端口的输入/输出（I / O）设备中，启动I / O端口旋转的周期，其中循环的每个端口旋转包括使 将至少一个I / O端口从一个CPU分配给多个CPU的不同CPU。 在所示实施例中，多个CPU中的每个CPU的I / O端口分配被旋转至少一部分周期。 可以根据具体应用实现其它特征和方面。
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公开(公告)号：US08825915B2
公开(公告)日：2014-09-02
申请号：US13418234
申请日：2012-03-12
CPC分类号： G06F13/366 , G06F3/06 , G06F3/061 , G06F3/0613 , G06F3/0635 , G06F3/0655 , G06F3/067 , G06F13/385
摘要： In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.
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公开(公告)号：US20130238818A1
公开(公告)日：2013-09-12
申请号：US13470137
申请日：2012-05-11
IPC分类号： G06F3/00
CPC分类号： G06F13/366 , G06F3/06 , G06F3/061 , G06F3/0613 , G06F3/0635 , G06F3/0655 , G06F3/067 , G06F13/385
摘要： In one aspect of the present description, in an input/output (I/O) device having multiple CPUs and multiple I/O ports, a cycle of I/O port rotations is initiated in which each port rotation of the cycle includes rotating an assignment of at least one I/O port from one CPU to a different CPU of a plurality of the CPUs. In the illustrated embodiment, an I/O port assignment for each CPU of the plurality CPUs is rotated for at least a portion of the cycle. Other features and aspects may be realized, depending upon the particular application.
摘要翻译： 在本说明书的一个方面，在具有多个CPU和多个I / O端口的输入/输出（I / O）设备中，启动I / O端口旋转的周期，其中循环的每个端口旋转包括使 将至少一个I / O端口从一个CPU分配给多个CPU的不同CPU。 在所示实施例中，多个CPU中的每个CPU的I / O端口分配被旋转至少一部分周期。 可以根据具体应用实现其它特征和方面。
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