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    Dual Damascene Process for Forming Vias and Interconnects in an Integrated Circuit Structure
    21.
    发明申请
    Dual Damascene Process for Forming Vias and Interconnects in an Integrated Circuit Structure 审中-公开

    公开(公告)号：US20190096751A1

    公开(公告)日：2019-03-28

    申请号：US16103538

    申请日：2018-08-14

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Hiroki Sato ,  Bonnie Hamlin ,  Andrew Taylor ,  Bomy Chen ,  Brian Hennes

    IPC: H01L21/768

    Abstract: A method of forming interconnects in a semiconductor device is provided. A mask including first and second openings is formed over a non-conductive structure. An etch is performed through the mask openings to define (a) a via trench having a via trench width and (b) an interconnect trench having a smaller width than the via trench width. A fill layer is deposited over the structure and (a) fills only a partial width of the via trench to thereby define via trench cavity and (b) fills the full width of the interconnect trench. A further etch is performed through the via trench cavity to form a via opening extending downwardly from the via trench. The remaining fill layer material is removed. The interconnect trench, via trench, and via opening are metallized to form a trench interconnect, a via interconnect, and a via extending downwardly from the via interconnect.

    Sidewall-type memory cell
    22.
    发明授权
    Sidewall-type memory cell 有权

    公开(公告)号：US10056545B2

    公开(公告)日：2018-08-21

    申请号：US15262923

    申请日：2016-09-12

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Hiroki Sato ,  Bomy Chen ,  Sonu Daryanani

    IPC: H01L45/00

    CPC classification number: H01L45/1226 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/1675

    Abstract: A sidewall-type memory cell (e.g., a CBRAM, ReRAM, or PCM cell) may include a bottom electrode, a top electrode layer defining a sidewall, and an electrolyte layer arranged between the bottom and top electrode layers, such that a conductive path is defined between the bottom electrode and a the top electrode sidewall via the electrolyte layer, wherein the bottom electrode layer extends generally horizontally with respect to a horizontal substrate, and the top electrode sidewall extends non-horizontally with respect to the horizontal substrate, such that when a positive bias-voltage is applied to the cell, a conductive path grows in a non-vertical direction (e.g., a generally horizontal direction or other non-vertical direction) between the bottom electrode and the top electrode sidewall.

    EEPROM MEMORY CELL WITH LOW VOLTAGE READ PATH AND HIGH VOLTAGE ERASE/WRITE PATH
    23.
    发明申请
    EEPROM MEMORY CELL WITH LOW VOLTAGE READ PATH AND HIGH VOLTAGE ERASE/WRITE PATH 有权
    具有低电压读取路径和高电压擦除/写入路径的EEPROM存储器单元

    公开(公告)号：US20140269102A1

    公开(公告)日：2014-09-18

    申请号：US14209275

    申请日：2014-03-13

    Applicant: Microchip Technology Incorporated

    Inventor： Kent Hewitt ,  Jack Wong ,  Bomy Chen ,  Sonu Daryanani ,  Jeffrey A. Shields ,  Daniel Alvarez ,  Mel Hymas

    IPC: G11C16/10

    CPC classification number: G11C16/0416 ,  H01L29/42328 ,  H01L29/7881

    Abstract: An electrically erasable programmable read only memory (EEPROM) cell may include a substrate including at least one active region, a floating gate adjacent the substrate, a write/erase gate defining a write/erase path for performing high voltage write and erase operations, and a read gate defining a read path for performing low voltage read operations, wherein the read path is distinct from the write/erase path. This allows for a smaller read gate oxide, thus allowing the cell size to be reduced. Further, the EEPROM cell may include two independently controllable read gates, thereby defining two independent transistors which allows better programming voltage isolation. This allows the memory array to be drawn using a common source instead of each column of EEPROM cells needing its own source line. This makes the array more scalable because the cell x-dimension would otherwise be limited by each column needing two metal 1 pitches.

    Abstract translation: 电可擦除可编程只读存储器（EEPROM）单元可以包括：衬底，其包括至少一个有源区域，与衬底相邻的浮置栅极;限定用于执行高电压写入和擦除操作的写/擦除路径的写/擦除栅极;以及 限定用于执行低电压读取操作的读取路径的读取门，其中读取路径与写/擦除路径不同。 这允许更小的读栅极氧化物，从而允许电池尺寸减小。 此外，EEPROM单元可以包括两个可独立控制的读取门，从而限定两个独立的晶体管，其允许更好的编程电压隔离。 这允许使用公共源而不是需要其自己的源极线的每一列EEPROM单元来绘制存储器阵列。 这使得阵列更具可扩展性，因为单元格x维度否则将受到需要两个金属1间距的每列限制。

    Resistive Memory Cell with Reduced Bottom Electrode
    24.
    发明申请
    Resistive Memory Cell with Reduced Bottom Electrode 审中-公开
    具有底部电极的电阻记忆单元

    公开(公告)号：US20140264247A1

    公开(公告)日：2014-09-18

    申请号：US14183792

    申请日：2014-02-19

    Applicant: Microchip Technology Incorporated

    Inventor： Sonu Daryanani ,  Bomy Chen

    IPC: H01L45/00

    CPC classification number: H01L45/16 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/145

    Abstract: A resistive memory cell may include a ring-shaped bottom electrode, a top electrode, and an electrolyte layer arranged between the bottom and top electrodes. A ring-shaped bottom electrode may be formed by forming a dielectric layer over a bottom electrode contact, etching a via in the dielectric layer to expose at least a portion of the bottom electrode contact, depositing a conductive via liner over the dielectric layer and into the via, the via liner deposited in the via forming a ring-shaped structure in the via and a contact portion in contact with the exposed bottom electrode contact, the ring-shaped structure defining a radially inward cavity of the ring-shaped structure, and filling the cavity with a dielectric fill material, such that the ring-shaped structure of the via liner forms the ring-shaped bottom electrode, depositing an electrolyte layer over the bottom electrode, and depositing a top electrode over the electrolyte layer.

    Abstract translation: 电阻式存储单元可以包括环形底部电极，顶部电极和布置在底部电极和顶部电极之间的电解质层。 可以通过在底部电极接触件上形成介电层来形成环形底部电极，蚀刻电介质层中的通孔以暴露底部电极接触的至少一部分，在电介质层上沉积导电通孔衬垫，并将其导入 所述通孔，沉积在所述通孔中的所述通孔衬垫在所述通孔中形成环形结构，以及与所述暴露的底部电极接触件接触的接触部分，所述环形结构限定所述环形结构的径向向内的腔，以及 用介电填充材料填充空腔，使得通孔衬垫的环形结构形成环形底部电极，在底部电极上沉​​积电解质层，并在电解质层上沉积顶部电极。

    Integrated circuit bond pad with multi-material toothed structure
    25.
    发明授权
    Integrated circuit bond pad with multi-material toothed structure 有权

    公开(公告)号：US12205910B2

    公开(公告)日：2025-01-21

    申请号：US18141621

    申请日：2023-05-01

    Applicant: Microchip Technology Incorporated

    Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Gerald Marsico ,  Julius Kovats

    IPC: H01L21/60 ,  H01L23/00

    Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.

    INTERPOSER WITH LINES HAVING PORTIONS SEPARATED BY BARRIER LAYERS
    26.
    发明公开
    INTERPOSER WITH LINES HAVING PORTIONS SEPARATED BY BARRIER LAYERS 审中-公开

    公开(公告)号：US20240321760A1

    公开(公告)日：2024-09-26

    申请号：US18369310

    申请日：2023-09-18

    Applicant: Microchip Technology Incorporated

    Inventor： Steve Nagel ,  Bomy Chen

    IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065

    CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L23/5383 ,  H01L25/0655

    Abstract: Interposers and methods for making interposers having a substrate having a surface defining a plane; a first portion of a metal line directly or indirectly supported by the substrate; a barrier layer on the first portion of the metal line; a second portion of the metal line on the first barrier layer, wherein the second portion is opposite the first portion across the barrier layer. The method includes etching a line pattern in a first portion of a metal layer through a first photoresist layer to form a first portion of a metal line, depositing a barrier layer on the first portion of the metal line, and etching a line pattern in a second portion of the metal layer through a second photoresist layer to form a second portion of a metal line wherein the second portion is opposite the first portion across the barrier layer.

    METHOD FOR FABRICATING A PATTERNED FD-SOI WAFER
    28.
    发明公开
    METHOD FOR FABRICATING A PATTERNED FD-SOI WAFER 审中-公开

    公开(公告)号：US20240170325A1

    公开(公告)日：2024-05-23

    申请号：US18200688

    申请日：2023-05-23

    Applicant: Microchip Technology Incorporated

    Inventor： Steve Nagel ,  Bomy Chen

    IPC: H01L21/762 ,  H01L27/12

    CPC classification number: H01L21/76251 ,  H01L27/1203

    Abstract: Methods for preparing a donor silicon wafer by applying a SiGe layer on a silicon substrate wafer, depositing a silicon layer on the SiGe layer, etching the silicon layer to form an opening in the silicon layer, wet etching the SiGe layer through the opening in the silicon layer to partially remove SiGe material from the SiGe layer and preserve the silicon layer, depositing a buried oxide layer on the silicon layer, etching the buried oxide layer to form a body bias area, and depositing silicon in the body bias area; bonding a recipient handle wafer to the etched buried oxide layer of the donor silicon wafer to define a BOX; and wet etching the SiGe layer to release the donor silicon wafer from the recipient handle wafer.

    Vapor cells and related systems and methods
    29.
    发明授权
    Vapor cells and related systems and methods 有权

    公开(公告)号：US11764796B2

    公开(公告)日：2023-09-19

    申请号：US17678655

    申请日：2022-02-23

    Applicant: Microchip Technology Incorporated

    Inventor： Robert Lutwak ,  Bomy Chen

    IPC: G04F5/14 ,  H03L7/26

    CPC classification number: H03L7/26

    Abstract: Vapor cells may include a body including a cavity within the body. A first substrate bonded to a second substrate at an interface within the body, at least one of the first substrate, the second substrate, or an interfacial material between the first and second substrates may define at least one recess or pore in a surface. A smallest dimension of the at least one recess or pore may be about 500 microns or less, as measured in a direction parallel to at least one surface of the first substrate partially defining the cavity.

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