公开(公告)号：US10553336B2

公开(公告)日：2020-02-04

申请号：US16034423

申请日：2018-07-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Greg Stom

IPC: H01C17/07 ,  H01C17/075 ,  H01C7/00 ,  H01C17/28 ,  H01C17/00 ,  H01C1/142

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure is provided. A TFR trench may be formed in an oxide layer. A resistive TFR layer may be deposited over the structure and extending into the trench. Portions of the TFR layer outside the trench may be removed by CMP to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region. At least one CMP may be performed to remove all or portions of the oxide layer and at least a partial height of the TFR ridges. A pair of spaced-apart metal interconnects may then be formed over opposing end regions of the TFR element, wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a resistor between the metal interconnects via the TFR element.

公开(公告)号：US20190392967A1

公开(公告)日：2019-12-26

申请号：US16034423

申请日：2018-07-13

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato ,  Greg Stom

IPC: H01C17/075 ,  H01C7/00 ,  H01C1/142 ,  H01C17/00 ,  H01C17/28

Abstract: A method for manufacturing a thin film resistor (TFR) module in an integrated circuit (IC) structure is provided. A TFR trench may be formed in an oxide layer. A resistive TFR layer may be deposited over the structure and extending into the trench. Portions of the TFR layer outside the trench may be removed by CMP to define a TFR element including a laterally-extending TFR bottom region and a plurality of TFR ridges extending upwardly from the laterally-extending TFR bottom region. At least one CMP may be performed to remove all or portions of the oxide layer and at least a partial height of the TFR ridges. A pair of spaced-apart metal interconnects may then be formed over opposing end regions of the TFR element, wherein each metal interconnect contacts a respective upwardly-extending TFR ridge, to thereby define a resistor between the metal interconnects via the TFR element.

公开(公告)号：US12040282B2

公开(公告)日：2024-07-16

申请号：US17667275

申请日：2022-02-08

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Anu Ramamurthy ,  Julius Kovats

IPC: H01L23/538 ,  H01L25/00 ,  H01L25/10 ,  H01L23/498 ,  H01R12/73

CPC classification number: H01L23/5385 ,  H01L25/105 ,  H01L25/50 ,  H01L23/49811 ,  H01L2225/1023 ,  H01L2225/107 ,  H01R12/737

Abstract: An electronic device includes a first interposer, a first integrated circuit (IC) device affixed to the first interposer, a second interposer, and a second IC device affixed to the second interposer. he second interposer is bonded to the first interposer. The first interposer includes first interposer circuitry and a first connection element electrically connected to the first interposer circuitry. The second interposer includes second interposer circuitry and a second connection element electrically connected to the second interposer circuitry. The second connection element is bonded to the first connection element to define a connection element pair. The connection element pair provides an electrical connection between the first interposer circuitry and the second interposer circuitry.

公开(公告)号：US11935824B2

公开(公告)日：2024-03-19

申请号：US17665749

申请日：2022-02-07

Applicant: Microchip Technology Incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Yaojian Leng ,  Julius Kovats

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/50 ,  H01L25/0652

Abstract: An integrated circuit package module includes an integrated circuit package device including a contact element, and a bonding system formed on the integrated circuit package device. The bonding system includes a bonding system substrate and a bonding element formed in the bonding system substrate and conductively coupled to the contact element of the integrated circuit package device. The bonding element includes (a) a conduction component conductively connected to the contact element, the conduction component formed from a first metal having a first melting point, and (b) a bonding component formed from a second metal having a second melting point lower than the first melting point of the first metal.

公开(公告)号：US20230352398A1

公开(公告)日：2023-11-02

申请号：US18218197

申请日：2023-07-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/528 ,  H01L21/67 ,  H01L21/66 ,  H01L23/522

CPC classification number: H01L23/5223 ,  H01L21/67259 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/40

Abstract: An array of metal-oxide-metal (MOM) capacitors formed in an integrated circuit (IC) structure may be used for evaluating misalignments between patterned layers of the IC structure. The array of MOM capacitors may be formed in a selected set of patterned layers, e.g., a via layer formed between a pair of metal interconnect layers. The MOM capacitors may be programmed with different patterned layer alignments (e.g., built in to photomasks or reticles used to form the patterned layers) to define an array of different alignments. When the MOM capacitors are formed on the wafer, the actual patterned layer alignments capacitors may differ from the programmed layer alignments due a process-related misalignment. The MOM capacitors may be subjected to electrical testing to identify this process-related misalignment, which may be used for initiating a correcting action, e.g., adjusting a manufacturing process or discarding misaligned IC structures or devices.

公开(公告)号：US11682642B2

公开(公告)日：2023-06-20

申请号：US17019768

申请日：2020-09-14

Applicant: Microchip Technology incorporated

Inventor： Justin Sato ,  Bomy Chen ,  Andrew Taylor

IPC: H01L23/00 ,  H01L23/10 ,  H01L21/768

CPC classification number: H01L24/09 ,  H01L21/768 ,  H01L21/76802 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/49 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05019 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/386 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/05099 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: An integrated circuit chip (die) may include a force mitigation system for reducing or mitigating under-pad stresses typically caused by wire bonding. The IC die may include wire bond pads and a force mitigation system formed below each wire bond pad. The force mitigation system may include a “shock plate” (e.g., metal region), a sealing layer located above the shock plate, and a force mitigation layer including an array of sealed voids between the metal region and the sealing layer. The sealed voids in the force mitigation layer may be defined by forming openings in an oxide dielectric layer and forming a non-conformal sealing layer over the openings to define an array of sealed voids. The force mitigation system may mitigate stresses caused by a wire bond on each wire bond pad, which may reduce or eliminate wire-bond-related damage to semiconductor devices located in the under-pad regions of the die.

公开(公告)号：US11626474B2

公开(公告)日：2023-04-11

申请号：US17170975

申请日：2021-02-09

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L49/02

Abstract: A thin film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a TFR element connected between first and second vertically-extending TFR side contacts. The TFR element includes a base portion extending laterally between the TFR side contacts, and first and second TFR element end flanges projecting vertically from opposing ends of the base portion. The first TFR element end flange is formed on a sidewall of the first TFR side contact, and the second TFR element end flange is formed on a sidewall of the second TFR side contact. A first TFR head contacts the first TFR side contact and a top of the first TFR element end flange, and a second TFR head contacts the second TFR side contact and a top of the second TFR element end flange, thus defining two parallel conductive paths between the TFR element and each TFR head.

公开(公告)号：US20230096226A1

公开(公告)日：2023-03-30

申请号：US18074617

申请日：2022-12-05

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L49/02 ,  H01L23/522

Abstract: A three-dimensional metal-insulator-metal (MIM) capacitor is formed in an integrated circuit structure. The 3D MIM capacitor may include a bottom conductor including a bottom plate portion (e.g., formed in a metal interconnect layer) and vertically-extending sidewall portions extending from the bottom plate portion. An insulator layer is formed on the bottom plate portion and the vertically extending sidewall portions of the bottom conductor. A top conductor is formed over the insulating layer, such that the top conductor is capacitively coupled to both the bottom plate portion and the vertically extending sidewall portions of the bottom conductor, to thereby define an increased area of capacitive coupling between the top and bottom conductors. The vertically extending sidewall portions of the bottom conductor may be formed in a single metal layer or by components of multiple metal layers.

公开(公告)号：US20220208954A1

公开(公告)日：2022-06-30

申请号：US17170975

申请日：2021-02-09

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L49/02

Abstract: A thin film resistor (TFR) module is formed in an integrated circuit device. The TFR module includes a TFR element connected between first and second vertically-extending TFR side contacts. The TFR element includes a base portion extending laterally between the TFR side contacts, and first and second TFR element end flanges projecting vertically from opposing ends of the base portion. The first TFR element end flange is formed on a sidewall of the first TFR side contact, and the second TFR element end flange is formed on a sidewall of the second TFR side contact. A first TFR head contacts the first TFR side contact and a top of the first TFR element end flange, and a second TFR head contacts the second TFR side contact and a top of the second TFR element end flange, thus defining two parallel conductive paths between the TFR element and each TFR head.

公开(公告)号：US20210384122A1

公开(公告)日：2021-12-09

申请号：US17117288

申请日：2020-12-10

Applicant: Microchip Technology Incorporated

Inventor： Yaojian Leng ,  Justin Sato

IPC: H01L23/522 ,  H01L23/532 ,  H01L49/02 ,  H01F27/28 ,  H01F27/32

Abstract: A low-resistance thick-wire integrated inductor may be formed in an integrated circuit (IC) device. The integrated inductor may include an elongated inductor wire defined by a metal layer stack including an upper metal layer, middle metal layer, and lower metal layer. The lower metal layer may be formed in a top copper interconnect layer, the upper metal layer may be formed in an aluminum bond pad layer, and the middle metal layer may comprise a copper tub region formed between the aluminum upper layer and copper lower layer. The wide copper region defining the middle layer of the metal layer stack may be formed concurrently with copper vias of interconnect structures in the IC device, e.g., by filling respective openings using copper electrochemical plating or other bottom-up fill process. The elongated inductor wire may be shaped in a spiral or other symmetrical or non-symmetrical shape.