公开(公告)号：US10861765B2

公开(公告)日：2020-12-08

申请号：US16431988

申请日：2019-06-05

Applicant: Micron Technology, Inc.

Inventor： James M. Derderian ,  Andrew M. Bayless ,  Xiao Li

IPC: H01L23/367 ,  H01L23/532 ,  H01L23/498 ,  H01L21/683 ,  B32B43/00 ,  B32B7/12

Abstract: A semiconductor device assembly having a semiconductor device attached to a substrate with a foil layer on a surface of the substrate. A layer of adhesive connects the substrate to a first surface of the semiconductor device. The semiconductor device assembly enables processing on the second surface of the semiconductor device. An energy pulse may be applied to the foil layer causing an exothermic reaction to the foil layer that releases the substrate from the semiconductor device. The semiconductor device assembly may include a release layer positioned between the foil layer and the layer of adhesive that connects the substrate to the semiconductor device. The heat generated by the exothermic reaction breaks down the release layer to release the substrate from the semiconductor device. The energy pulse may be an electric charge, a heat pulse, or may be applied from a laser.

公开(公告)号：US10749071B2

公开(公告)日：2020-08-18

申请号：US16397627

申请日：2019-04-29

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless

IPC: H01L29/40 ,  H01L21/00 ,  H01L33/00 ,  H01L21/78 ,  H01L23/538 ,  H01L21/683 ,  H01L21/304

Abstract: A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.

公开(公告)号：US10403598B2

公开(公告)日：2019-09-03

申请号：US15674850

申请日：2017-08-11

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Joseph M. Brand

IPC: H01L23/00 ,  H01L21/683

Abstract: Methods of detaching semiconductor device structures from carrier structures may involve directing a laser through a carrier structure comprising a semiconductor material to a barrier material located between the carrier structure and a semiconductor device structure adhere to an opposite side of the barrier material. A bond between the carrier structure and an adhesive material temporarily securing the carrier structure to the semiconductor device structure may be released in response to heating of the barrier material by the laser beam. The carrier structure may be removed from the semiconductor device structure, the barrier material removed, and an adhesive bonding the semiconductor device structure to the barrier material removed.

公开(公告)号：US20190252575A1

公开(公告)日：2019-08-15

申请号：US16397627

申请日：2019-04-29

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless

IPC: H01L33/00 ,  H01L21/78 ,  H01L23/538

Abstract: A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.

公开(公告)号：US10163693B1

公开(公告)日：2018-12-25

申请号：US15851304

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  James M. Derderian ,  Xiao Li

IPC: H01L21/304 ,  H01L21/306 ,  H01L23/28 ,  H01L21/768 ,  H01L21/02 ,  H01L23/29

Abstract: A method for processing semiconductor dice comprises removing material from a surface of a semiconductor wafer to create a pocket surrounded by a sidewall at a lateral periphery of the semiconductor wafer, forming a film on a bottom of the pocket and securing semiconductor dice to the film in mutually spaced locations. A dielectric molding material is placed in the pocket over and between the semiconductor dice, material is removed from another surface of the semiconductor wafer to expose the film, bond pads of the semiconductor dice are exposed, redistribution layers in electrical communication with the bond pads of associated semiconductor dice are formed, and the redistribution layers and associated semiconductor dice are singulated along spaces between the semiconductor dice.

公开(公告)号：US20230317511A1

公开(公告)日：2023-10-05

申请号：US18111496

申请日：2023-02-17

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz ,  Owen R. Fay

IPC: H01L21/768 ,  H01L21/02 ,  G03F7/004 ,  G03F7/20

CPC classification number: H01L21/76801 ,  G03F7/004 ,  G03F7/20 ,  H01L21/02348

Abstract: A method for smoothing structures formed of curable materials on a semiconductor device includes applying a layer of photo-responsive material on a substrate. The photo-responsive material is exposed to ultraviolet light through a grayscale gradient mask. Subsequent to removing unwanted portions of the photo-responsive material, the photo-responsive material that remains on the substrate is cured. During the curing process, the temperature is increased from a starting temperature to a final cure temperature over a first time period that allows the photo-responsive material to cross-flow. The temperature of the photo-responsive material is maintained at approximately the final cure temperature for a second time period, and then the temperature of the photo-responsive material is decreased to a predetermined finish temperature over a third time period.

公开(公告)号：US11676955B2

公开(公告)日：2023-06-13

申请号：US16898180

申请日：2020-06-10

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Bradley R. Bitz

IPC: H01L21/78 ,  H01L21/70 ,  H01L21/82 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/70 ,  H01L21/78 ,  H01L21/82 ,  H01L24/29 ,  H01L25/0652

Abstract: A method for separating semiconductor die stacks of a chip-on-wafer assembly is disclosed herein. In one example, divider walls are arranged in a pattern on a first surface of a device wafer such that regions between the divider walls define mounting sites. Die stacks are mounted to the device wafer, wherein individual die stacks are located at a corresponding mounting site between the divider walls. The device wafer is cut through from a second surface that is opposite the first surface of the device wafer, and the divider walls are removed from between the die stacks to form a vacant lane between adjacent die stacks.

公开(公告)号：US11515171B2

公开(公告)日：2022-11-29

申请号：US16895751

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Xiaopeng Qu ,  Hyunsuk Chun ,  Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L21/447 ,  H01L21/67 ,  H01L21/033 ,  B23K20/02

Abstract: This patent application relates to methods and apparatus for temperature modification and reduction of contamination in bonding stacked microelectronic devices with heat applied from a bond head of a thermocompression bonding tool. The stack is substantially enclosed within a skirt carried by the bond head to reduce heat loss and contaminants from the stack, and heat may be added from the skirt.

公开(公告)号：US20220344161A1

公开(公告)日：2022-10-27

申请号：US17241386

申请日：2021-04-27

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Brandon P. Wirz

IPC: H01L21/265 ,  H01L21/768 ,  H01L21/324

Abstract: A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.

公开(公告)号：US20220336366A1

公开(公告)日：2022-10-20

申请号：US17231210

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Brandon P. Wirz ,  Andrew M. Bayless

IPC: H01L23/532 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L21/78 ,  H01L25/00

Abstract: Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.