公开(公告)号：US09627295B2

公开(公告)日：2017-04-18

申请号：US15059020

申请日：2016-03-02

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Jian He ,  Lalapet Rangan Vasudevan ,  Kyle K. Kirby ,  Hongqi Li

IPC: H01L23/48 ,  H01L21/76 ,  H01L23/52 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/481 ,  H01L21/76801 ,  H01L21/76838 ,  H01L21/76898 ,  H01L23/522 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

公开(公告)号：US20150243583A1

公开(公告)日：2015-08-27

申请号：US14188367

申请日：2014-02-24

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Gowrisankar Damarla ,  Shyam Ramalingam

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/367

CPC classification number: H01L23/481 ,  H01L21/7682 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.

Abstract translation: 根据一些实施例的半导体器件包括延伸穿过衬底结构的至少一部分的衬底结构和导电互连。 导电互连可以包括通过硅通孔和应力消除特征，其适应材料的热膨胀和/或热收缩以管理半导体器件中的内部应力。 根据一些实施例的制造半导体器件的方法包括去除导电互连的材料以形成应力消除间隙。

公开(公告)号：US09099442B2

公开(公告)日：2015-08-04

申请号：US13959429

申请日：2013-08-05

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Shyam Ramalingam

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device includes a substrate having an opening that extends at least partially through the substrate. A conductive material having a positive coefficient of thermal expansion (CTE) partially fills the opening. A negative thermal expansion (NTE) having a negative CTE also partially fills the opening. In one embodiment, the conductive material includes copper and the NTE material includes zirconium tungstate.

Abstract translation: 本文公开了具有并入负扩张（NTE）材料的互连的半导体器件。 在一个实施例中，半导体器件包括具有至少部分延伸穿过衬底的开口的衬底。 具有正的热膨胀系数（CTE）的导电材料部分地填充开口。 具有负CTE的负热膨胀（NTE）也部分填充开口。 在一个实施例中，导电材料包括铜，NTE材料包括钨酸锆。

公开(公告)号：US20150145146A1

公开(公告)日：2015-05-28

申请号：US14612926

申请日：2015-02-03

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Anurag Jindal ,  Irina Vasilyeva

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76865 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5384 ,  H01L2924/0002 ,  Y10S438/927 ,  H01L2924/00

Abstract: Methods of exposing conductive vias of semiconductor devices may involve positioning a barrier material over conductive vias extending from a backside surface of a substrate to at least substantially conform to the conductive vias. A self-planarizing isolation material may be positioned on a side of the barrier material opposing the substrate. An exposed surface of the self-planarizing isolation material may be at least substantially planar. A portion of the self-planarizing isolation material, a portion of the barrier material, and a portion of at least some of the conductive vias may be removed to expose each of the conductive vias. Removal may be stopped after exposing at least one laterally extending portion of the barrier material proximate the substrate.

Abstract translation: 暴露半导体器件的导电通路的方法可包括将阻挡材料定位在从衬底的背面延伸至至少基本上符合导电通孔的导电通孔上。 自平面化隔离材料可以位于与衬底相对的阻挡材料的一侧上。 自平坦化隔离材料的暴露表面可以至少基本上是平面的。 可以去除自平坦化隔离材料的一部分，阻挡材料的一部分和至少一些导电通孔的一部分，以暴露每个导电通孔。 在将阻挡材料的至少一个横向延伸的部分暴露在基底附近之前可以停止移除。

公开(公告)号：US20150044860A1

公开(公告)日：2015-02-12

申请号：US14524631

申请日：2014-10-27

Applicant: Micron Technology, Inc.

Inventor： Anurag Jindal ,  Gowri Damarla ,  Roger W. Lindsay ,  Eric Blomiley

IPC: H01L21/28 ,  H01L27/115

CPC classification number: H01L29/40114 ,  H01L21/02057 ,  H01L21/32134 ,  H01L27/11556

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatuses that include them. In one such method, a silicide is formed in a tier of silicon, the silicide is removed, and a device is formed at least partially in a void that was occupied by the silicide. One such apparatus includes a tier of silicon with a void between tiers of dielectric material. Residual silicide is on the tier of silicon and/or on the tiers of dielectric material and a device is formed at least partially in the void. Additional embodiments are also described.

Abstract translation: 描述形成多层半导体器件的方法以及包括它们的器件。 在一种这样的方法中，硅化物形成在硅层中，硅化物被去除，并且器件至少部分地形成在被硅化物占据的空隙中。 一种这样的设备包括一层硅，在介电材料层之间具有空隙。 残余硅化物位于硅层和/或介电材料层上，并且至少部分地在空隙中形成器件。 还描述了另外的实施例。