公开(公告)号：US20200266203A1

公开(公告)日：2020-08-20

申请号：US16277311

申请日：2019-02-15

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US20250096202A1

公开(公告)日：2025-03-20

申请号：US18788541

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Wei Zhou

IPC: H01L25/065 ,  H01L23/00 ,  H10B80/00

Abstract: A semiconductor device assembly is provided. The semiconductor device assembly includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die, and a second plurality of stacked memory dies mounted on and electrically coupled with the first plurality of stacked memory dies. A first dielectric material is disposed around the first plurality of stacked memory dies. A second dielectric material is disposed at the first dielectric material and surrounding the second plurality of stacked memory dies. A third dielectric material is disposed between the first plurality of stacked memory dies and the second plurality of stacked memory dies and between the first dielectric material and the second dielectric material.

公开(公告)号：US20250096171A1

公开(公告)日：2025-03-20

申请号：US18789049

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/683 ,  H01L23/48 ,  H01L23/544 ,  H01L25/065 ,  H10B80/00

Abstract: A method of forming a semiconductor wafer is provided. The method includes dicing wafers into dies, testing the dies for known good dies, and bonding known good dies to a carrier wafer to form a top KGD wafer. The method also includes filling gaps between top dies to form a top gap-fill layer around and above each of the top dies, and bonding the top dies with a dummy silicon wafer. The method also includes bonding known good dies to carrier wafers to form one or more core KGD wafers, as well as filling gaps between the core dies to form a core gap-fill layer around each of the core dies. The method then includes bonding the one or more core KGD wafers to the top KGD wafer to form a KGD wafer stack.

公开(公告)号：US12255163B2

公开(公告)日：2025-03-18

申请号：US17666437

申请日：2022-02-07

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Keizo Kawakita ,  Bret K. Street

IPC: H01L23/00 ,  H01L25/065

Abstract: Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.

公开(公告)号：US20250079366A1

公开(公告)日：2025-03-06

申请号：US18788588

申请日：2024-07-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Bret K. Street ,  Akshay N. Singh ,  Kunal R. Parekh ,  Bharat Bhushan

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor device assembly with layered dielectric is disclosed. The semiconductor device assembly includes a first semiconductor die and a second semiconductor die coupled with the first semiconductor die. The second semiconductor die is at least partially surrounded by a tensile dielectric and a compressive dielectric disposed at the first semiconductor die. The tensile dielectric is configured to experience tensile stress at an upper surface and compressive stress at a lower surface (e.g., the tensile dielectric will warp concave down). In contrast, the compressive dielectric is configured to experience compressive stress at an upper surface and tensile stress at a lower surface (e.g., the compressive dielectric will warp concave up). As a result, stress in the semiconductor device assembly can be reduced and overall yield can be improved.

公开(公告)号：US20240421030A1

公开(公告)日：2024-12-19

申请号：US18674664

申请日：2024-05-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Amy R. Griffin ,  Kunal R. Parekh ,  Akshay N. Singh

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor device is provided. The semiconductor device includes a logic die, a first plurality of stacked memory dies electrically coupled with the logic die at a first location above a back side surface of the logic die, a second plurality of stacked memory dies electrically coupled with the logic die at a second location above the back side surface of logic die, a first dielectric material disposed above the back side surface of the logic die and between the first plurality of stacked memory dies and the second plurality of stacked memory dies, and a dummy die disposed above the first dielectric material and coupled to the first plurality of stacked memory dies and the second plurality of stacked memory dies, wherein the dummy die is coupled to back side surfaces of the first plurality and second plurality of stacked memory dies through a second dielectric layer having dielectric-dielectric fusion bonding.

公开(公告)号：US20240014170A1

公开(公告)日：2024-01-11

申请号：US17857304

申请日：2022-07-05

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Akshay N. Singh ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L24/05 ,  H01L24/06 ,  H01L25/50 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L24/96 ,  H01L2224/96 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L24/92 ,  H01L2224/92125 ,  H01L2224/9222

Abstract: A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.

公开(公告)号：US11450645B2

公开(公告)日：2022-09-20

申请号：US17103486

申请日：2020-11-24

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Pratap Murali ,  Raj K. Bansal

IPC: H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

Abstract: Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.

公开(公告)号：US11177269B2

公开(公告)日：2021-11-16

申请号：US16277311

申请日：2019-02-15

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  Chris M. Carlson ,  Collin Howder

IPC: H01L27/11556 ,  G11C8/14 ,  G11C16/04 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/11558 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11524

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. First charge-blocking material is formed to extend elevationally along the vertically-alternating tiers. The first charge-blocking material has k of at least 7.0 and comprises a metal oxide. A second charge-blocking material is formed laterally inward of the first charge-blocking material. The second charge-blocking material has k less than 7.0. Storage material is formed laterally inward of the second charge-blocking material. Insulative charge-passage material is formed laterally inward of the storage material. Channel material is formed to extend elevationally along the insulative tiers and the wordline tiers laterally inward of the insulative charge-passage material. Structure embodiments are disclosed.

公开(公告)号：US11121144B2

公开(公告)日：2021-09-14

申请号：US16682544

申请日：2019-11-13

Applicant: Micron Technology, Inc.

Inventor： Bharat Bhushan ,  David Daycock ,  Subramanian Krishnan ,  Leroy Ekarista Wibowo

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11573 ,  H01L21/311 ,  H01L21/3213 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11519

Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating first tiers and second tiers. First insulator material is above the stack. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel-material strings are in and upwardly project from an uppermost material that is directly above the stack. Conducting material is directly against laterally-inner sides of individual of the upwardly-projecting channel-material strings and project upwardly from the individual upwardly-projecting channel-material strings. A ring comprising insulating material is formed individually circumferentially about the upwardly-projecting conducting material. Second insulator material is formed above the first insulator material, the ring, and the upwardly-projecting conducting material. The first and second insulator materials comprise different compositions relative one another. Conductive vias are formed in the second insulator material that are individually directly electrically coupled to the individual channel-material strings through the upwardly-projecting conducting material. Other embodiments, including structure, are disclosed.