公开(公告)号：US20220020422A1

公开(公告)日：2022-01-20

申请号：US16932567

申请日：2020-07-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Toru Ishikawa ,  Minari Arai ,  Nobuki Takahashi

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4096

Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.

公开(公告)号：US20200118608A1

公开(公告)日：2020-04-16

申请号：US16436655

申请日：2019-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Akira Yamashita ,  Shuichi Murai ,  Kohei Nakamura

IPC: G11C7/22 ,  H03K5/15 ,  G11C11/4076

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

公开(公告)号：US10339998B1

公开(公告)日：2019-07-02

申请号：US15937552

申请日：2018-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/1534 ,  H03K5/05 ,  H03K3/037 ,  H03K5/135 ,  H03K5/00

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

公开(公告)号：US20190074838A1

公开(公告)日：2019-03-07

申请号：US16177821

申请日：2018-11-01

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa

IPC: H03K19/0185 ,  H03K19/00

Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.

公开(公告)号：US10128847B2

公开(公告)日：2018-11-13

申请号：US15055230

申请日：2016-02-26

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa

IPC: H03L5/00 ,  H03K19/0185 ,  H03K19/00

Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.

公开(公告)号：US20170250689A1

公开(公告)日：2017-08-31

申请号：US15055230

申请日：2016-02-26

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K19/018507

Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.

公开(公告)号：US09729131B2

公开(公告)日：2017-08-08

申请号：US14866250

申请日：2015-09-25

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa

IPC: H03K5/156

CPC classification number: H03K5/1565 ,  H03K5/159

Abstract: Apparatuses and methods for correcting a duty cycle of a clock signal are described. An example apparatus includes: a duty cycle corrector (DCC) that receives an input clock signal and a control signal and produces an output clock signal responsive, at least in part, to the input clock signal and the control signal; a circuit that divides a frequency of the input clock signal by a positive even integer and generates an intermediate clock signal; and a phase detector that generates the control signal responsive, at least in part, to a difference in phase between the output clock signal and the intermediate clock signal.

公开(公告)号：US09590606B2

公开(公告)日：2017-03-07

申请号：US14318067

申请日：2014-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Hiroki Takahashi

IPC: H03K5/156

CPC classification number: H03K5/1565

Abstract: Disclosed herein is a device includes a duty correction circuit adjusting a duty ratio of a first clock signal based on a duty control signal to generate a second clock signal; a delay line delaying the second clock signal to generate a third clock signal; and a duty cycle detector detecting the duty ratio of the second clock signal to generate the duty control signal in a first mode, and detecting the duty ratio of the third clock signal to generate the duty control signal in a second mode.

Abstract translation: 本文公开了一种装置，包括：占空比校正电路，其基于占空比控制信号调整第一时钟信号的占空比，以产生第二时钟信号; 延迟线延迟所述第二时钟信号以产生第三时钟信号; 以及占空比检测器检测第二时钟信号的占空比以在第一模式中产生占空比控制信号，并且检测第三时钟信号的占空比以在第二模式中产生占空比控制信号。

公开(公告)号：US09559710B2

公开(公告)日：2017-01-31

申请号：US14745118

申请日：2015-06-19

Applicant: Micron Technology, Inc.

Inventor： Katsuhiro Kitagawa

IPC: H03K3/03 ,  H03L7/099 ,  H03L7/10 ,  H03L7/081 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: H03L7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  H03K3/0315 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0997 ,  H03L7/0998

Abstract: According to the present invention, a ring oscillator coupled to an output node operable to output a clock signal including a first logic level generated by a first odd number of delay circuits, and a second logic level different from the first logic level generated by a second odd number of delay circuits different from the first odd number of delay circuits.

Abstract translation: 根据本发明，耦合到输出节点的环形振荡器可操作以输出包括由第一奇数个延迟电路产生的第一逻辑电平的时钟信号和与第二逻辑电平产生的第二逻辑电平不同的第二逻辑电平 与第一奇数个延迟电路不同的奇数个延迟电路。