公开(公告)号：US12010847B2

公开(公告)日：2024-06-11

申请号：US17691993

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Matthew J. King ,  John D. Hopkins ,  M. Jared Barclay

IPC: H10B43/27 ,  H01L23/48 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/481 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

公开(公告)号：US20230055422A1

公开(公告)日：2023-02-23

申请号：US17409476

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

公开(公告)号：US11302710B2

公开(公告)日：2022-04-12

申请号：US16739332

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Matthew J. King ,  John D. Hopkins ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L23/48

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

公开(公告)号：US11271002B2

公开(公告)日：2022-03-08

申请号：US16382932

申请日：2019-04-12

Applicant: Micron Technology, Inc.

Inventor： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L21/311 ,  H01L27/11582 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US20210217766A1

公开(公告)日：2021-07-15

申请号：US16739332

申请日：2020-01-10

Applicant: Micron Technology, Inc.

Inventor： Darwin A. Clampitt ,  Matthew J. King ,  John D. Hopkins ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L23/48 ,  H01L27/11526 ,  H01L27/11519 ,  H01L27/11573 ,  H01L27/11565

Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.

公开(公告)号：US20190267397A1

公开(公告)日：2019-08-29

申请号：US16410992

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/423 ,  H01L29/51 ,  H01L29/792

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.

公开(公告)号：US20180358377A1

公开(公告)日：2018-12-13

申请号：US16102987

申请日：2018-08-14

Applicant: Micron Technology, Inc.

Inventor： Chris M. Carlson ,  M. Jared Barclay

IPC: H01L27/11582 ,  H01L29/792 ,  H01L29/51 ,  H01L29/423 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/512 ,  H01L29/518 ,  H01L29/7926

Abstract: Some embodiments include a memory cell which has, in the following order; a control gate, charge-blocking material, charge-trapping material, a first oxide, a charge-passage structure, a second oxide, and channel material. The charge-passage structure has a central region sandwiched between first and second regions. The central region has a lower probability of trapping charges and/or a lower rate of trapping charges than the first and second regions. Some embodiments include an integrated structure having a vertical stack of alternating conductive levels and insulative levels, and having a charge-passage structure extending vertically along the vertical stack. Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and wordline levels, and having a charge-passage structure extending vertically along the vertical stack.