公开(公告)号：US20240304250A1

公开(公告)日：2024-09-12

申请号：US18668021

申请日：2024-05-17

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C16/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/56 ,  G11C16/26 ,  G11C16/0483

Abstract: A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.

公开(公告)号：US11869595B2

公开(公告)日：2024-01-09

申请号：US18085228

申请日：2022-12-20

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen ,  Phong Sy Nguyen

IPC: G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C16/30

CPC classification number: G11C16/10 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/26 ,  G11C16/30

Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

公开(公告)号：US20230137866A1

公开(公告)日：2023-05-04

申请号：US17974799

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Violante Moschiano ,  James Fitzpatrick ,  Kishore Kumar Muccherla ,  Jeffrey S. McNeil ,  Phong Sy Nguyen

IPC: G06F3/06

Abstract: A memory device comprising an array of memory cells organized into a set of sub-blocks and a set of wordlines. Control logic is operatively coupled with the array of memory cells, the control logic to perform operations including: receiving a program command from a processing device, the program command including information indicative of a physical address associated with a retired wordline of the set of wordlines; in response to detecting the information within the program command, generating dummy data that is one of pseudo-random data, all one values, or all zero values; and causing the dummy data to be programmed to memory cells of multiple sub-blocks of the set of sub-blocks that are selectively connected to the retired wordline.

公开(公告)号：US20230012648A1

公开(公告)日：2023-01-19

申请号：US17841096

申请日：2022-06-15

Applicant: Micron Technology, Inc.

Inventor： James Fitzpatrick ,  Phong Sy Nguyen ,  Dung Viet Nguyen ,  Sivagnanam Parthasarathy

IPC: G11C16/34 ,  G11C16/26

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

公开(公告)号：US20230005552A1

公开(公告)日：2023-01-05

申请号：US17940317

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C16/34 ,  G11C7/10 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.

公开(公告)号：US11462265B2

公开(公告)日：2022-10-04

申请号：US17127459

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/10

Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of values of the data bits according to a mapping between combinations of values of bits and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. XOR (or XNOR) is used to combine the data bits into bits of a group identification of a first group, among the plurality of groups, that contains the first level. The memory device reads, using the group identification, the data bits back from the first memory cell to finely program the threshold voltage of the memory cell to represent the data bits.

公开(公告)号：US20220310164A1

公开(公告)日：2022-09-29

申请号：US17216015

申请日：2021-03-29

Applicant: Micron Technology, Inc.

Inventor： Dung V. Nguyen ,  Phong Sy Nguyen

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C7/10

Abstract: A command to program data to a memory device is received. Target charge levels of a set of memory cells in the memory device for a first programming step are determined based on the data. A first set of indicators are provided to the memory device. The first set of indicators indicate the target charge levels for the first programming step. Target charge levels of the set of memory cells for a second programming step are determined based on the data. A second set of indicators are provided to the memory device. The second set of indicators indicate the target charge levels for the second programming step.

公开(公告)号：US11456038B2

公开(公告)日：2022-09-27

申请号：US17127476

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/30 ,  G11C7/10 ,  G11C16/26 ,  G11C16/10

Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between combinations of bit values and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. A group identification of a first group, among the plurality of groups, containing the first level is determined for the memory cell. The memory device reads, using the group identification, a subset of the data bits back from the first memory cell, and combines the bits of the group identification and the subset to recover the entire set of data bits to finely program the threshold voltage of the memory cell to represent the data bits.

公开(公告)号：US11430526B2

公开(公告)日：2022-08-30

申请号：US17127413

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/30 ,  G11C16/26

Abstract: In a coarse programming, the threshold voltage of the memory cell is programmed to a first level representative of N−1 bit values data according to a first mapping between combinations of values of N−1 possible bits and threshold levels. A group identification is representative of whether the first level is an odd or even numbered level in the first mapping. For a fine programming, the memory cell is read, based on the group identification, to obtain the N−1 bit values; and at least one additional bit is received to join the N−1 bit values to form at least N bit values. The threshold voltage of the memory cell is then finely programmed to a second level representative of the at least N bit values according to a second mapping between combinations of values of the at least N possible bits and threshold levels.

公开(公告)号：US20220199165A1

公开(公告)日：2022-06-23

申请号：US17247643

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C16/20 ,  G11C16/26 ,  G11C16/30

Abstract: Control logic in a memory device identifies a first plurality of groups of programming distributions, wherein each group comprises a subset of programming distributions associated with a portion of a memory array of the memory device configured as quad-level (QLC) memory. During a first pass of a multi-pass programming operation, the control logic coarsely programs memory cells in the portion configured as QLC memory to initial values representing a second plurality of pages of host data and stores, in a portion of the memory array of the memory device configured as single-level cell (SLC) memory, an indicator of the first plurality of groups of programming distributions with which each of the coarsely programmed memory cells is associated. During a second pass of the multi-pass programming operation, the control logic reads the coarsely programmed initial values from the first pass based on the indicator of the first plurality of groups of programming distributions and finely programs the memory cells in the portion configured as QLC memory to final values representing the second plurality of pages of host data.