公开(公告)号：US11886358B2

公开(公告)日：2024-01-30

申请号：US17717452

申请日：2022-04-11

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Balint Fleischer

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06 ,  G06F12/02 ,  G06F13/40

CPC classification number: G06F13/1668 ,  G06F12/0246 ,  G06F12/063 ,  G06F13/4068 ,  G06F13/4221

Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.

公开(公告)号：US11861207B2

公开(公告)日：2024-01-02

申请号：US17562329

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Chandra M. Guda ,  Suresh Rajgopal

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0608 ,  G06F3/0659 ,  G06F3/0673

Abstract: A processing device determines a duration for executing a portion of an erase operation based on a plurality of execution times of erase operations performed on a memory device. The processing device executes the portion of the erase operation. Responsive to detecting expiration of the duration for executing the erase operation, the processing logic executes an erase suspend operation to suspend the erase operation. Responsive to detecting completion of the erase suspend operation, the processing logic executes one or more commands. The processing device further executes an erase resume operation to resume the erase operation on the memory device.

公开(公告)号：US20230359390A1

公开(公告)日：2023-11-09

申请号：US17735583

申请日：2022-05-03

Applicant: Micron Technology, Inc.

Inventor： Jose Rey C. De Luna ,  Suresh Rajgopal ,  Jeremy Wayne Butterfield ,  Dustin J. Carter

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0659 ,  G06F3/0629 ,  G06F3/0604 ,  G06F3/0679

Abstract: Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide a configurable buffer device. The configuration buffer device is coupled between a processing device and a set of memory components. The configurable buffer device can be configured based on configuration data to couple a first quantity of front-side channels to a second quantity of back-side channels. The configuration data can be received from an external source, such as the processing device, or can be stored in a configuration register at manufacture. The configuration data can also be generated or determined based on one or more pins of the buffer device that control how many font-side channels and how many back-side channels to enable/disable.

公开(公告)号：US20230350587A1

公开(公告)日：2023-11-02

申请号：US18137002

申请日：2023-04-20

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Liang Yu ,  Jonathan S. Parry ,  Chulbum Kim ,  Daniel J. Hubbard ,  Suresh Rajgopal

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0658 ,  G06F3/0679

Abstract: A memory device includes memory dies, each memory die including a memory array and control logic, operatively coupled with the memory array, to perform peak power management (PPM) operations. The PPM operations include receiving a request to perform an operation, determining whether to initiate a PPM priority override procedure, and in response to determining to initiate the PPM priority override procedure, performing the PPM priority override procedure to execute the operation. Performing the PPM priority override procedure includes reconfiguring each high current breakpoints as a respective low current breakpoint to execute the operation.

公开(公告)号：US11301401B1

公开(公告)日：2022-04-12

申请号：US17127289

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Balint Fleischer

IPC: G06F13/12 ,  G06F13/16 ,  G06F13/42 ,  G06F12/06 ,  G06F12/02 ,  G06F13/40

Abstract: An apparatus includes a memory component having a plurality of ball grid array (BGA) components, wherein each respective one of the BGA components includes a plurality of memory blocks and a BGA component controller and firmware adjacent the plurality of memory blocks to manage the plurality of memory blocks. The apparatus further includes a processing device, included in the memory component, to perform memory operations on the BGA components.

公开(公告)号：US11182087B2

公开(公告)日：2021-11-23

申请号：US16662943

申请日：2019-10-24

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Zhi Kai Feng ,  Yue Wei

IPC: G06F3/06 ,  G06F12/02

Abstract: A memory device protection manager determines an estimated remaining life of a physical memory device. By comparing the estimated remaining life of the physical memory device to a threshold value, the memory device protection manager determines whether a drive protection condition has been triggered. When the drive protection condition is triggered, the memory device protection manager modifies a write performance for subsequent data units to a modified write performance rate. The modified write performance rate is an upper limit on the write performance for the subsequent data units.

公开(公告)号：US20210173580A1

公开(公告)日：2021-06-10

申请号：US16709614

申请日：2019-12-10

Applicant: Micron Technology, Inc.

Inventor： Chandra M. Guda ,  Suresh Rajgopal

IPC: G06F3/06

Abstract: A processing device receives a request to perform an erase operation on a memory device. The processing device executes a portion of the erase operation during a first time period. The processing device further executes an erase suspend operation to suspend the erase operation during the first time period. Responsive to detecting a completion of the erase suspend operation, the processing device receives one or more commands directed to the memory device. The processing device also executes the one or more commands during a second time period. Responsive to the expiration of the second time period, the processing device executes an erase resume operation to resume the erase operation on the memory device.

公开(公告)号：US20210055979A1

公开(公告)日：2021-02-25

申请号：US17092778

申请日：2020-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Suresh Rajgopal ,  Dan E. Soto ,  Steven Eskildsen

IPC: G06F11/07 ,  G06F12/02 ,  G06F13/10

Abstract: Apparatus having a plurality of sets of memory devices and a multiplexer, wherein each set of memory devices of the plurality of sets of memory devices corresponds to a respective enable signal of a plurality of enable signals, wherein, for each set of memory devices of the plurality of sets of memory devices, each memory device of that set of memory devices is configured to receive commands in response to the respective enable signal for that set of memory devices having a particular logic level, and wherein, for each set of memory devices of the plurality of sets of memory devices, the multiplexer is configured to selectively connect input/output signal lines of that set of memory devices to an interface of the apparatus in response to the respective enable signal for that set of memory devices.

公开(公告)号：US20190354301A1

公开(公告)日：2019-11-21

申请号：US15982978

申请日：2018-05-17

Applicant: Micron Technology, Inc.

Inventor： Suresh Rajgopal ,  Henrico L. Yahja ,  Steven Eskildsen ,  Dustin J. Carter

IPC: G06F3/06

Abstract: A selection device can be operatively coupled with non-volatile memory devices. Enable signals that are based on an architecture of non-volatile memory devices can be received. Data can be transmitted to the non-volatile memory devices based on the enable signals that are based on the architecture of the non-volatile memory devices.