公开(公告)号：US11038027B2

公开(公告)日：2021-06-15

申请号：US16294759

申请日：2019-03-06

Applicant: Micron Technology, inc.

Inventor： Kamal M. Karda ,  Deepak Chandra Pandey ,  Haitao Liu ,  Richard J. Hill ,  Guangyu Huang ,  Yunfei Gao ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/267 ,  H01L29/786 ,  H01L27/108 ,  H01L29/207 ,  H01L29/08 ,  H01L29/16

Abstract: Some embodiments include an integrated assembly having a polycrystalline first semiconductor material, and having a second semiconductor material directly adjacent to the polycrystalline first semiconductor material. The second semiconductor material is of a different composition than the polycrystalline first semiconductor material. A conductivity-enhancing dopant is within the second semiconductor material. The conductivity-enhancing dopant is a neutral-type dopant relative to the polycrystalline first semiconductor material. An electrical gate is adjacent to a region of the polycrystalline first semiconductor material and is configured to induce an electric field within said region of the polycrystalline first semiconductor material. The gate is not adjacent to the second semiconductor material.

公开(公告)号：US10998440B2

公开(公告)日：2021-05-04

申请号：US16596407

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Ramanathan Gandhi ,  Hong Li ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Sanh D. Tang ,  Scott E. Sills

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.

公开(公告)号：US20190067437A1

公开(公告)日：2019-02-28

申请号：US16118064

申请日：2018-08-30

Applicant: Micron Technology, Inc.

Inventor： Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Scott E. Sills

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device is disclosed. The semiconductor device includes a transistor including a source contact, a drain contact, and a channel region including an oxide semiconductor material as the channel material. At least one of the drain contact or the source contact include a conductive material, such as Ruthenium, to reduce the Schottky effects at the interface with the channel material.

公开(公告)号：US20250098228A1

公开(公告)日：2025-03-20

申请号：US18966496

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/51 ,  H10B51/20 ,  H10B53/20

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US12218236B2

公开(公告)日：2025-02-04

申请号：US18050424

申请日：2022-10-27

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Ramanathan Gandhi ,  Durai Vishak Nirmal Ramaswamy ,  Yi Fang Lee ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H10B63/00

Abstract: A transistor comprises a first conductive contact, a heterogeneous channel comprising at least one oxide semiconductor material over the first conductive contact, a second conductive contact over the heterogeneous channel, and a gate electrode laterally neighboring the heterogeneous channel. A device, a method of forming a device, a memory device, and an electronic system are also described.

公开(公告)号：US12199182B2

公开(公告)日：2025-01-14

申请号：US17472895

申请日：2021-09-13

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Kirk D. Prall ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/51 ,  H10B51/20 ,  H10B53/20

Abstract: A device comprises an array comprising rows and columns of elevationally-extending transistors. An access line interconnects multiple of the elevationally-extending transistors along individual of the rows. The transistors individually comprise an upper source/drain region, a lower source/drain region, and a channel region extending elevationally there-between. The channel region comprises an oxide semiconductor. A transistor gate is operatively laterally-proximate the channel region and comprises a portion of an individual of the access lines. Intra-row-insulating material is longitudinally between immediately-intra-row-adjacent of the elevationally-extending transistors. Inter-row-insulating material is laterally between immediately-adjacent of the rows of the elevationally-extending transistors. At least one of the intra-row-insulating material and the inter-row-insulating material comprises void space. Other embodiments, including method embodiments, are disclosed.

公开(公告)号：US20240413154A1

公开(公告)日：2024-12-12

申请号：US18807741

申请日：2024-08-16

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US12133383B2

公开(公告)日：2024-10-29

申请号：US18506889

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Venkatakrishnan Sriraman ,  Dae Hong Eom ,  Ramanathan Gandhi ,  Donghua Li ,  Ashok Kumar Muthukumaran

IPC: H01L29/788 ,  H01L29/66 ,  H01L29/792 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792 ,  H10B43/27

Abstract: A memory cell comprises channel material, charge-passage material, programmable material, a charge-blocking region, and a control gate. The programmable material comprises at least two regions comprising SiNx having a region comprising SiOy therebetween, where “x” is 0.5 to 3.0 and “y” is 1.0 to 3.0. Methods are disclosed.

公开(公告)号：US20240081053A1

公开(公告)日：2024-03-07

申请号：US18506889

申请日：2023-11-10

Applicant: Micron Technology, Inc.

Inventor： Venkatakrishnan Sriraman ,  Dae Hong Eom ,  Ramanathan Gandhi ,  Donghua Li ,  Ashok Kumar Muthukumaran

IPC: H10B41/27 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/792 ,  H10B43/27

Abstract: A memory cell comprises channel material, charge-passage material, programmable material, a charge-blocking region, and a control gate. The programmable material comprises at least two regions comprising SiNx having a region comprising SiOy therebetween, where “x” is 0.5 to 3.0 and “y” is 1.0 to 3.0. Methods are disclosed.

公开(公告)号：US20240074216A1

公开(公告)日：2024-02-29

申请号：US18387921

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Yi Fang Lee ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Ramanathan Gandhi ,  Karthik Sarpatwari ,  Scott E. Sills ,  Sameer Chhajed

IPC: H10B99/00 ,  H01L27/092 ,  H01L27/12 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H10B99/00 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66969 ,  H01L29/78642 ,  H01L29/7869

Abstract: Some embodiments include an integrated assembly having a first semiconductor material between two regions of a second semiconductor material. The second semiconductor material is a different composition than the first semiconductor material. Hydrogen is diffused within the first and second semiconductor materials. The conductivity of the second semiconductor material increases in response to the hydrogen diffused therein to thereby create a structure having the second semiconductor material as source/drain regions, and having the first semiconductor material as a channel region between the source/drain regions. A transistor gate is adjacent the channel region and is configured to induce an electric field within the channel region. Some embodiments include methods of forming integrated assemblies.