公开(公告)号：US09460978B1

公开(公告)日：2016-10-04

申请号：US13864243

申请日：2013-04-17

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/58 ,  H01L23/34 ,  H01L29/40

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer overlying the first transistors and including second transistors; wherein the second layer includes a through layer via with a diameter of less than 150 nm; and a Phase-Lock-Loop (PLL) circuit, where the Phase-Lock-Loop (PLL) circuit is connected to at least one input structure, and where the least one input structure is designed to connect an input to the device from external devices.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 覆盖所述第一晶体管并包括第二晶体管的第二层; 其中所述第二层包括直径小于150nm的贯通层通孔; 以及锁相环（PLL）电路，其中锁相环（PLL）电路连接到至少一个输入结构，并且其中至少一个输入结构被设计为将外部连接到设备的输入 设备。

公开(公告)号：US20160204085A1

公开(公告)日：2016-07-14

申请号：US15079017

申请日：2016-03-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 至少一个金属层，提供所述多个第一晶体管的至少一部分之间的互连; 第二层厚度小于2微米，第二层包括多个第二晶体管，第二层覆盖至少一个金属层; 以及构造成向第二晶体管的一部分提供功率的至少一个导电结构，其中所述提供功率由至少一个晶体管控制。

公开(公告)号：US09030858B2

公开(公告)日：2015-05-12

申请号：US13624968

申请日：2012-09-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Paul Lim

IPC: G11C11/34 ,  H01L27/108 ,  G11C5/02 ,  G11C5/06 ,  H01L27/06 ,  H01L29/78 ,  G11C11/406 ,  H01L23/00 ,  H01L27/02

CPC classification number: H01L27/10873 ,  G11C5/025 ,  G11C5/063 ,  G11C11/406 ,  G11C2211/4016 ,  H01L24/16 ,  H01L24/94 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7841 ,  H01L29/785 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一半导体层，其中所述第一晶体管通过包括铝或铜的至少一个金属层互连; 以及包括第二晶体管并覆盖所述至少一个金属层的第二单结晶半导体层，其中所述至少一个金属层位于所述第一半导体层和所述第二单结晶半导体层之间，其中所述第二单结晶半导体层 半导体层的厚度小于100nm，其中第二晶体管包括水平取向的晶体管。

公开(公告)号：US08703597B1

公开(公告)日：2014-04-22

申请号：US13869963

申请日：2013-04-25

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/82 ,  H01L21/822

CPC classification number: H01L21/76898 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/082 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/785 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a second semiconductor layer over the first layer; fabricating a plurality of memory cell control lines where the control lines include a portion of the second layer; where the second layer includes second transistors, where the second transistors include a mono-crystalline semiconductor, and where the second transistors are configured to be memory cells.

Abstract translation: 一种制造器件的方法，所述方法包括：提供包括第一晶体管的第一层，其中所述第一晶体管包括单晶半导体; 在第一层上覆盖第二半导体层; 制造多个存储单元控制线，其中控制线包括第二层的一部分; 其中第二层包括第二晶体管，其中第二晶体管包括单晶半导体，并且其中第二晶体管被配置为存储单元。

公开(公告)号：US08574929B1

公开(公告)日：2013-11-05

申请号：US13678584

申请日：2012-11-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L21/477

CPC classification number: H01L27/0688 ,  H01L21/76254 ,  H01L27/088 ,  H01L27/092

Abstract: A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.

Abstract translation: 一种形成单片3D器件的方法，包括：处理包括第一单晶晶体管的第一层; 通过使用离子切割层转印在包括第一单晶体晶体管的第一层的顶部上转移第二单晶层; 并通过光学退火修复由离子切割引起的损伤。

公开(公告)号：US20230260826A1

公开(公告)日：2023-08-17

申请号：US18138110

申请日：2023-04-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/74

CPC classification number: H01L21/743

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid including at least one second transistor, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

公开(公告)号：US11670536B2

公开(公告)日：2023-06-06

申请号：US18092253

申请日：2022-12-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/48 ,  H01L21/74

CPC classification number: H01L21/743

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

公开(公告)号：US20230142628A1

公开(公告)日：2023-05-11

申请号：US18092253

申请日：2022-12-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/74

CPC classification number: H01L21/743

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors) atop the third metal layer; a fourth metal layer disposed above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid, which includes the fifth metal layer; a local power distribution grid, which includes the second metal layer, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer.

公开(公告)号：US20220406424A1

公开(公告)日：2022-12-22

申请号：US17739339

申请日：2022-05-09

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar

IPC: G16H15/00 ,  G06F40/40 ,  G06F3/01 ,  G10L15/26 ,  G06F40/186

Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

公开(公告)号：US20220336231A1

公开(公告)日：2022-10-20

申请号：US17846010

申请日：2022-06-22

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/34 ,  H01L27/02 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/098 ,  H01L23/522 ,  H01L23/367 ,  H01L27/092 ,  H01L25/00 ,  H01L23/60 ,  H01L25/065

Abstract: A method for producing a 3D semiconductor device: providing a first level with a first single crystal layer; forming a plurality of first transistors in and/or on the first level with a first metal layer above; forming a second metal layer above the first metal layer; forming a third metal layer above the second metal layer; forming at least one second level on top of or above the third metal layer; performing a first etch step; performing additional processing steps to form a plurality of second transistors within the second level; forming a fourth metal layer above; forming a connection to the second metal layer which includes a via through the second level; forming a fifth metal layer above, where some second transistors include a metal gate, and the fifth metal layer thickness is at least 50% greater than the second metal layer thickness.