公开(公告)号：US10903803B2

公开(公告)日：2021-01-26

申请号：US16785482

申请日：2020-02-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Kenichi Nagura

IPC: H01L29/06 ,  H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56 ,  H01L23/31 ,  H01L23/29 ,  H01L23/538 ,  H01L25/16 ,  H01L21/8252

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US10778159B2

公开(公告)日：2020-09-15

申请号：US16192890

申请日：2018-11-16

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Satoshi Tanaka ,  Takayuki Tsutsui ,  Yasunari Umemoto

IPC: H03F3/21 ,  H01L21/82 ,  H03F3/19 ,  H03F1/56 ,  H03F1/02 ,  H01L27/06 ,  H01L21/8252

Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted.

公开(公告)号：US10707200B2

公开(公告)日：2020-07-07

申请号：US16219886

申请日：2018-12-13

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Takayuki Tsutsui ,  Isao Obu ,  Yasuhisa Yamamoto

IPC: H01L27/02 ,  H03F3/213 ,  H01L23/00 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H03F1/52 ,  H03F3/195 ,  H01L29/861 ,  H01L29/06 ,  H01L29/737

Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

公开(公告)号：US10192862B2

公开(公告)日：2019-01-29

申请号：US15902815

申请日：2018-02-22

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kenji Sasaki ,  Takayuki Tsutsui ,  Isao Obu ,  Yasuhisa Yamamoto

IPC: H01L27/02 ,  H03F3/213 ,  H01L23/00 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

公开(公告)号：US20180240725A1

公开(公告)日：2018-08-23

申请号：US15899010

申请日：2018-02-19

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L21/52 ,  H01L21/67

Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.

公开(公告)号：US09130004B2

公开(公告)日：2015-09-08

申请号：US14088510

申请日：2013-11-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Atsushi Kurokawa

IPC: H01L29/73 ,  H01L29/66 ,  H01L29/737 ,  H01L21/8252 ,  H01L27/06

CPC classification number: H01L29/7304 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0658 ,  H01L29/66242 ,  H01L29/7371 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/1305 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A heterojunction bipolar transistor includes a ballast resistor layer of which resistance increases with an increase in temperature. The ballast resistor layer includes a first ballast resistor sub-layer having a positive temperature coefficient of resistivity in a first temperature range and a second temperature range and a second ballast resistor sub-layer having a negative temperature coefficient of resistivity in the first temperature range and a positive temperature coefficient of resistivity in the second temperature range.

Abstract translation: 异质结双极晶体管包括电阻随温度升高而增加的镇流电阻层。 镇流电阻层包括在第一温度范围内具有正电温度系数和第二温度范围的第一镇流电阻子层和在第一温度范围内具有负电阻率温度系数的第二镇流电阻子层，以及 在第二温度范围内的正电阻率温度系数。

公开(公告)号：US11626511B2

公开(公告)日：2023-04-11

申请号：US16207084

申请日：2018-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao Obu ,  Yasunari Umemoto ,  Masahiro Shibata ,  Shigeki Koya ,  Masao Kondo ,  Takayuki Tsutsui

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L23/00

Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

公开(公告)号：US11424350B2

公开(公告)日：2022-08-23

申请号：US17109897

申请日：2020-12-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Shigeki Koya ,  Isao Obu

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/205

Abstract: A collector layer of an HBT includes a high-concentration collector layer and a low-concentration collector layer thereon. The low-concentration collector layer includes a graded collector layer in which the energy band gap varies to narrow with increasing distance from the base layer. The electron affinity of the semiconductor material for the base layer is greater than that of the semiconductor material for the graded collector layer at the point of the largest energy band gap by about 0.15 eV or less. The electron velocity in the graded collector layer peaks at a certain electric field strength. In the graded collector layer, the strength of the quasi-electric field, an electric field that acts on electrons as a result of the varying energy band gap, is between about 0.3 times and about 1.8 times the peak electric field strength, the electric field strength at which the electron velocity peaks.

公开(公告)号：US11329146B2

公开(公告)日：2022-05-10

申请号：US17386462

申请日：2021-07-27

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari Umemoto ,  Isao Obu ,  Kaoru Ideno ,  Shigeki Koya

IPC: H01L29/737 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06

Abstract: A collector layer, a base layer, and an emitter layer that are disposed on a substrate form a bipolar transistor. An emitter electrode is in ohmic contact with the emitter layer. The emitter layer has a shape that is long in one direction in plan view. A difference in dimension with respect to a longitudinal direction of the emitter layer between the emitter layer and an ohmic contact interface at which the emitter layer and the emitter electrode are in ohmic contact with each other is larger than a difference in dimension with respect to a width direction of the emitter layer between the emitter layer and the ohmic contact interface.

公开(公告)号：US11322462B2

公开(公告)日：2022-05-03

申请号：US16223597

申请日：2018-12-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takayuki Tsutsui ,  Isao Obu

IPC: H01L23/66 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L29/737 ,  H03F3/217 ,  H01L27/06 ,  H01L23/538 ,  H03F1/56 ,  H03F3/195 ,  H03H7/38

Abstract: A plurality of unit transistors that are connected in parallel to each other are formed on a substrate. In addition, a ground bump is provided on the substrate. A plurality of first capacitors are each provided for a corresponding one of the plurality of unit transistors and each connect an output electrode of the corresponding one of the plurality of unit transistors and the ground bump to each other.