公开(公告)号：US20230343749A1

公开(公告)日：2023-10-26

申请号：US17660441

申请日：2022-04-25

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Norazham Mohd Sukemi ,  Chin Teck Siong ,  Tsung Nan Lo ,  Wen Hung Huang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L23/49816 ,  H01L24/92 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/48227 ,  H01L2224/92247

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.

公开(公告)号：US20230187211A1

公开(公告)日：2023-06-15

申请号：US17546449

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/283 ,  H01L24/03 ,  H01L24/11 ,  H01L21/78 ,  H01L24/05 ,  H01L2224/02331 ,  H01L2224/0231 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.