公开(公告)号：US20240194486A1

公开(公告)日：2024-06-13

申请号：US18444826

申请日：2024-02-19

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/283 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

公开(公告)号：US20240030173A1

公开(公告)日：2024-01-25

申请号：US17867853

申请日：2022-07-19

Applicant: NXP B.V.

Inventor： Che Ming Fang ,  Kuan-Hsiang Mao ,  Yufu Liu ,  Wen Hung Huang

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/13 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/13027 ,  H01L2224/11849 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/73101

Abstract: An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.

公开(公告)号：US11640947B2

公开(公告)日：2023-05-02

申请号：US17333837

申请日：2021-05-28

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L23/00 ,  C09D5/24 ,  C09D179/04 ,  C09D179/08 ,  G03F7/09

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

公开(公告)号：US11935753B2

公开(公告)日：2024-03-19

申请号：US17546449

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/283 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

公开(公告)号：US20230187299A1

公开(公告)日：2023-06-15

申请号：US17546398

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Che Ming Fang ,  Yufu Liu ,  Wen Hung Huang

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1191 ,  H01L2224/05024 ,  H01L2224/13022

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

公开(公告)号：US20220384372A1

公开(公告)日：2022-12-01

申请号：US17333837

申请日：2021-05-28

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L23/00 ,  C09D5/24 ,  C09D179/04 ,  C09D179/08

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

公开(公告)号：US20250038138A1

公开(公告)日：2025-01-30

申请号：US18359945

申请日：2023-07-27

Applicant: NXP B.V.

Inventor： Ting Hsun Tu ,  Paul Southworth ,  Che Ming Fang

IPC: H01L23/00

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first non-conductive layer over a top side a semiconductor die and patterning the first non-conductive layer to form a collar structure surrounding an opening exposing a top surface of a bond pad. A second non-conductive layer is formed over the first non-conductive layer and exposed portions of the top side of the semiconductor die. The second non-conductive layer is different from the first non-conductive layer. The second non-conductive layer is patterned to expose the top surface of the bond pad and inner sidewalls of the of the collar structure surrounding the opening such that the second non-conductive layer does not contact the bond pad. A metal redistribution layer is formed over the second non-conductive layer and exposed top surface of the bond pad.

公开(公告)号：US12198998B2

公开(公告)日：2025-01-14

申请号：US17546398

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Che Ming Fang ,  Yufu Liu ,  Wen Hung Huang

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

公开(公告)号：US20230187211A1

公开(公告)日：2023-06-15

申请号：US17546449

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/283 ,  H01L24/03 ,  H01L24/11 ,  H01L21/78 ,  H01L24/05 ,  H01L2224/02331 ,  H01L2224/0231 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.