公开(公告)号：US20230187299A1

公开(公告)日：2023-06-15

申请号：US17546398

申请日：2021-12-09

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Che Ming Fang ,  Yufu Liu ,  Wen Hung Huang

IPC: H01L23/31 ,  H01L21/78 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3171 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/1191 ,  H01L2224/05024 ,  H01L2224/13022

Abstract: A method for manufacturing a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices. Each integrated circuit device extends into the semiconductor wafer to a first depth. Prior to singulation of the integrated circuit devices on the semiconductor wafer, the method further includes forming a cut between the integrated circuit devices. The cut extends to at least the first depth, but does not extend completely through the semiconductor wafer. The cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on each integrated circuit device, a passivation layer on a top surface and on the edges.

公开(公告)号：US20220384372A1

公开(公告)日：2022-12-01

申请号：US17333837

申请日：2021-05-28

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L23/00 ,  C09D5/24 ,  C09D179/04 ,  C09D179/08

Abstract: A packaging semiconductor device, such as a fan-out Wafer-Level Packaging (FOWLP) device, is fabricated by providing a semiconductor device (20) having conductive patterns (22) disposed on a first surface and then forming, on the conductive patterns, photoresist islands (24) having a first predetermined shape defined by a first critical width dimension and a minimum height dimension so that a subsequently-formed dielectric polymer layer (26) surrounds but does not cover each photoresist island (24), thereby allowing each photoresist island to be selectively removed from the one or more conductive patterns to form one or more via openings (28) in the dielectric polymer layer such that each via opening has a second predetermined shape which matches at least part of the first predetermined shape of the photoresist islands.

公开(公告)号：US20240387271A1

公开(公告)日：2024-11-21

申请号：US18787368

申请日：2024-07-29

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Yufu Liu

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

公开(公告)号：US20240194486A1

公开(公告)日：2024-06-13

申请号：US18444826

申请日：2024-02-19

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Che Ming Fang ,  Yufu Liu

IPC: H01L21/283 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/283 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/05558 ,  H01L2924/3511

Abstract: A method for forming a packaged integrated circuit device includes providing a semiconductor wafer having a plurality of integrated circuit devices, each integrated circuit device extending into the semiconductor wafer to a first depth, and grinding a backside of the silicon wafer to no more than the first depth. The method further includes forming a backside cut between the integrated circuit devices. The backside cut extends to within the first depth, but the backside cut does not extend completely through the semiconductor wafer. The backside cut exposes a plurality of edges of each of the integrated circuit devices. The method further includes depositing, on the backside of the wafer, a metallization layer on a bottom surface of the integrated circuit devices and on the edges.

公开(公告)号：US20240105659A1

公开(公告)日：2024-03-28

申请号：US17936042

申请日：2022-09-28

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Yufu Liu ,  Wen Hung Huang ,  Tsung Nan Lo

IPC: H01L23/00

CPC classification number: H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/13 ,  H01L2224/13006 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/73101

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over a semiconductor die. A portion of the RDL contacts a die pad of the semiconductor die. A metal layer is formed on a top surface and sidewalls of the RDL and configured to encase the RDL. A non-conductive layer is formed over the metal layer and underlying RDL. An opening in the non-conductive layer is formed exposing a portion of the metal layer formed on the RDL. An under-bump metallization (UBM) is formed in the opening and conductively connected to the die pad by way of the metal layer and RDL.

公开(公告)号：US20230014470A1

公开(公告)日：2023-01-19

申请号：US17377507

申请日：2021-07-16

Applicant: NXP B.V

Inventor： Kuan-Hsiang Mao ,  Wen Hung Huang ,  Yufu Liu

IPC: H01L21/78 ,  H01L23/31 ,  H01L21/56

Abstract: Packaged semiconductor devices are disclosed, comprising: a semiconductor die having a top major surface with a plurality of contact pads thereon, and four sides, wherein the sides are stepped such that a lower portion of each side extends laterally beyond a respective upper portion; encapsulating material encapsulating the top major surface and the upper portion of each of the sides wherein the semiconductor die is exposed at the lower portion of each of the sides; a contact-redistribution structure on the encapsulating material over the top major surface of the semiconductor die; a plurality of metallic studs extending through the encapsulating material, and providing electrical contact between the contact pads and the contact-redistribution structure. Corresponding methods are also disclosed.

公开(公告)号：US20240395674A1

公开(公告)日：2024-11-28

申请号：US18322658

申请日：2023-05-24

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Shu-Han Yang ,  Pey Fang Hiew ,  Wen Hung Huang

IPC: H01L23/49 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a redistribution layer (RDL) over an active side of a semiconductor die. A die pad of the semiconductor die is connected to an interconnect segment of the RDL by way of a bond wire. An encapsulating layer is formed over the active side of the semiconductor die such that exposed portions of the die pad and the bond wire are embedded in the encapsulating layer.

公开(公告)号：US20240030173A1

公开(公告)日：2024-01-25

申请号：US17867853

申请日：2022-07-19

Applicant: NXP B.V.

Inventor： Che Ming Fang ,  Kuan-Hsiang Mao ,  Yufu Liu ,  Wen Hung Huang

IPC: H01L23/00

CPC classification number: H01L24/20 ,  H01L24/13 ,  H01L24/11 ,  H01L24/19 ,  H01L24/73 ,  H01L2224/13027 ,  H01L2224/11849 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/73101

Abstract: An IC package includes one or more microelectronic devices, a plurality of package bumps disposed at a first side, and a metal structure electrically connecting at least a first device contact pad of a first microelectronic device and at least a first package bump of the plurality of package bumps. The metal structure includes an RDL trace extending between a first region aligned with the first device contact pad and a second region aligned with the first package bump, wherein the first package bump is mechanically and electrically connected directly to the second region of the RDL trace. The metal structure further includes a first via extending between the first region of the RDL trace and the first device contact pad and further includes a set of one or more support studs extending from the second region to a support surface facing the first side.

公开(公告)号：US20240014123A1

公开(公告)日：2024-01-11

申请号：US17810882

申请日：2022-07-06

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Chin Teck Siong ,  Pey Fang Hiew ,  Wen Yuan Chuang ,  Sharon Huey Lin Tay ,  Wen Hung Huang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L23/49838 ,  H01L21/4839 ,  H01L21/4882 ,  H01L23/3675 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/16245 ,  H01L23/49816 ,  H01L25/105

Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.

公开(公告)号：US20230326821A1

公开(公告)日：2023-10-12

申请号：US17658611

申请日：2022-04-08

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Wen Yuan Chuang ,  Wen Hung Huang

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/3128 ,  H01L21/565 ,  H01L21/568

Abstract: Five-side mold protection for semiconductor packages is described. In an illustrative, non-limiting embodiment, a semiconductor package may include: a substrate comprising a top surface, a bottom surface, and four sidewalls; an electrical component comprising a backside and a frontside, where the frontside of the electrical component is coupled to the top surface of the substrate; and a molding compound, where the molding compound encapsulates the backside of the electrical component and the four sidewalls of the substrate.