公开(公告)号：US20240014123A1

公开(公告)日：2024-01-11

申请号：US17810882

申请日：2022-07-06

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Chin Teck Siong ,  Pey Fang Hiew ,  Wen Yuan Chuang ,  Sharon Huey Lin Tay ,  Wen Hung Huang

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L23/49861 ,  H01L24/16 ,  H01L24/81 ,  H01L23/49838 ,  H01L21/4839 ,  H01L21/4882 ,  H01L23/3675 ,  H01L2224/81203 ,  H01L2224/81207 ,  H01L2224/16245 ,  H01L23/49816 ,  H01L25/105

Abstract: A method of forming a semiconductor device is provided. The method includes placing a semiconductor die and a leadframe on a carrier substrate. The semiconductor die includes a plurality of bond pads and the leadframe includes a plurality of leads. A first lead of the plurality of leads has a proximal end affixed to a first bond pad of the plurality of bond pads and a distal end placed on the carrier substrate. At least a portion of the semiconductor die and the leadframe is encapsulated with an encapsulant. The carrier substrate is separated from a first major side of the encapsulated semiconductor die and leadframe exposing a distal end portion of the first lead. A package substrate is applied on the first major side.

公开(公告)号：US12288770B2

公开(公告)日：2025-04-29

申请号：US17660441

申请日：2022-04-25

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Norazham Mohd Sukemi ,  Chin Teck Siong ,  Tsung Nan Lo ,  Wen Hung Huang

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.

公开(公告)号：US20250069903A1

公开(公告)日：2025-02-27

申请号：US18236481

申请日：2023-08-22

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Chin Teck Siong ,  Pey Fang Hiew ,  Wen Hung Huang

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/552

Abstract: A method of forming a semiconductor device is provided. The method includes forming a redistribution layer (RDL) substrate over an active side of a semiconductor die. The RDL substrate includes a plurality of under-bump metallization (UBM) structures. A die pad of a leadframe is affixed on a backside of the semiconductor die. The leadframe includes a plurality of leads having a first portion of each lead connected to the die pad and a second portion of each lead extending vertically along sidewalls of the semiconductor die toward a plane of the RDL substrate. An encapsulant encapsulates the semiconductor die and the leadframe, a lead tip portion of each lead is exposed through the encapsulant.

公开(公告)号：US20230369168A1

公开(公告)日：2023-11-16

申请号：US17740554

申请日：2022-05-10

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Chin Teck Siong ,  Wen Hung Huang

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L24/19 ,  H01L21/565 ,  H01L24/20 ,  H01L2224/214 ,  H01L2224/211 ,  H01L2224/2105 ,  H01L2224/2101 ,  H01L2924/182 ,  H01L2924/183 ,  H01L2924/3511 ,  H01L2924/3025

Abstract: An integrated circuit (IC) package includes one or more microelectronic devices disposed between a first side and an opposing second side of the IC package and further includes a metal frame structure comprising a metal layer disposed at the second side, an embedded ground plane (EGP) structure encircling the one or more microelectronic devices, and a set of stacked conductive structures extending from the EGP structure to the first side through a set of one or more redistribution layers at the first side. The IC package further can include an array of package contacts disposed at the first side and an encapsulant layer encapsulating the one or more microelectronic devices in a volume defined by an inner sidewall of the EGP structure.

公开(公告)号：US20230343749A1

公开(公告)日：2023-10-26

申请号：US17660441

申请日：2022-04-25

Applicant: NXP B.V.

Inventor： Kuan-Hsiang Mao ,  Norazham Mohd Sukemi ,  Chin Teck Siong ,  Tsung Nan Lo ,  Wen Hung Huang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L24/48 ,  H01L23/49816 ,  H01L24/92 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/48227 ,  H01L2224/92247

Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.