公开(公告)号：US09490782B2

公开(公告)日：2016-11-08

申请号：US14527865

申请日：2014-10-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: H03K3/3562 ,  H03K3/037 ,  H03K3/356 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract translation: 锁存电路基于主从交叉耦合逆变器对配置。 从电路的反相器耦合到高电压轨和低压轨，其中对于从电路逆变器对的两个反相器中的每一个，与一个电压轨的耦合通过电阻元件。 该电路设计避免了内部时钟缓冲器的需要，并且可以实现单相时钟，因此不需要内部时钟信号反相。 该电路可以实现低功耗，当输入和输出数据信号相同时，无冗余转换的动态功耗。

公开(公告)号：US10270448B1

公开(公告)日：2019-04-23

申请号：US15980882

申请日：2018-05-16

Applicant: NXP B.V.

Inventor： Kristof Blutman ,  Sebastien Antonius Josephus Fabrie ,  Juan Diego Echeverri Escobar ,  Ajay Kapoor ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

IPC: H03K19/0185

Abstract: A level shifter circuit is described herein for shifting a signal from a first voltage domain to a second voltage domain. The level shifter circuit includes two current paths between a supply terminal of the first voltage domain and a supply terminal of the second voltage domain. The first and second current paths each include a differential transistor that receives a signal from a pulse generator in a first voltage domain. The pulse generator provides pulses to the differential transistors based on an input signal to be translated to the second voltage domain. The level shifter includes a latch circuit in the second voltage domain that includes two inputs where each input is biased at a node of one of the current paths. Each current path includes a bias transistor whose control terminal receives a compensated biasing voltage for biasing the bias transistor. The compensated biasing voltage is compensated to account for drive strength variation of at least one transistor in each current path.

公开(公告)号：US20180212519A1

公开(公告)日：2018-07-26

申请号：US15412727

申请日：2017-01-23

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Steven Mark Thoen

IPC: H02M3/158

CPC classification number: H02M3/158 ,  G11C5/143 ,  G11C5/148 ,  H02M2001/0032 ,  H02M2001/0077 ,  Y02B70/16

Abstract: As may be consistent with one or more embodiments, an apparatus and or method involves a switching power supply circuit and a control circuit therefor. The switching power supply circuit operates in high and low-power modes. In the high power mode, high and low power rails of a first circuit and of a second circuit are coupled to a power source circuit (e.g. a battery). In the low-power mode, the first circuit is operated in a high power domain and the second circuit is operated in a low power domain using recycled charge from the high power domain. The control circuit operates the switching circuit in the high-power mode and low-power mode (for power conservation) in response to a control signal.

公开(公告)号：US20170039104A1

公开(公告)日：2017-02-09

申请号：US14820436

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Nur Engin ,  Steven Thoen ,  Jose Pineda de Gyvez

IPC: G06F11/10 ,  H03M13/35 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/353

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract translation: 根据本发明的一个实施例，公开了一种集成电路（IC）装置。 在该实施例中，IC器件包括SRAM模块，耦合到SRAM模块的封装逻辑，上下文源以及耦合到上下文源和封装逻辑的ECC简档控制器，ECC简档控制器被配置为选择ECC简档 响应于从上下文源接收的用于由包装器逻辑使用的上下文信息。

公开(公告)号：US20170012628A1

公开(公告)日：2017-01-12

申请号：US14794411

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Kristof Blutman ,  Ajay Kapoor ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03K19/0185

CPC classification number: H03K19/018514 ,  H03K3/356182 ,  H03K5/13 ,  H03K19/0185

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract translation: 本公开的方面涉及可以在每个域在不同电压范围上操作的堆叠布置中操作的相应功率域（电路）之间的通信。 第一电路提供基于从第一功率域接收的输入信号的转变而在第一和第二电压电平之间变化的差分输出。 第一和第二驱动器电路分别耦合到第一和第二差分输出。 第三驱动器电路与第一和第二电路一起工作，以响应于输入信号处于第二电压电平，通过驱动处于第二电压电平的输出电路来将输入信号从第一功率域电平移位到第二电源域上的输出信号 第一电压电平，并且响应于输入信号处于第二电压电平，将输出电路驱动在第三电压电平。

公开(公告)号：US20160098062A1

公开(公告)日：2016-04-07

申请号：US14504789

申请日：2014-10-02

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: G06F1/10

CPC classification number: G06F1/10 ,  H03K5/159 ,  H03K19/094

Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

Abstract translation: 本公开的方面涉及操作基于时间的电路。 可以结合一个或多个实施例来实现，一种装置和/或方法涉及检测在相应时钟域中工作的电路的定时特性，每个时钟域具有时钟信号路径经过的半导体主体区域。 各个半导体本体区域以各自的偏置电平被偏置，这些偏置电平是基于检测到的偏移半导体主体区域的时钟信号路径的定时特性。

公开(公告)号：US20150123722A1

公开(公告)日：2015-05-07

申请号：US14527865

申请日：2014-10-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: H03K3/3562 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract translation: 锁存电路基于主从交叉耦合逆变器对配置。 从电路的反相器耦合到高电压轨和低压轨，其中对于从电路逆变器对的两个反相器中的每一个，与一个电压轨的耦合通过电阻元件。 该电路设计避免了内部时钟缓冲器的需要，并且可以实现单相时钟，因此不需要内部时钟信号反相。 该电路可以实现低功耗，当输入和输出数据信号相同时，无冗余转换的动态功耗。

公开(公告)号：US08947149B1

公开(公告)日：2015-02-03

申请号：US14136137

申请日：2013-12-20

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Ralf Malzahn ,  Rinze Ida Mechtildis Peter Meijer ,  Peter Thueringer

IPC: G06F1/04 ,  H03K3/012

CPC classification number: H03K5/003 ,  G06F1/10

Abstract: Embodiments of a clock distribution device and a method of clock distribution are described. In one embodiment, a clock distribution device includes a stacked clock driver circuit configured to perform clock signal charge recycling on input clock signals that swing between different voltage ranges and a load circuit. The stacked clock driver circuit includes stacked driver circuits configured to generate output clock signals that swing between the different voltage ranges. The load circuit includes load networks of different semiconductor types. Each of the load networks are configured to be driven by one of the output clock signals. Other embodiments are also described.

Abstract translation: 时钟分配装置的实施例和时钟分配方法被描述。 在一个实施例中，时钟分配装置包括堆叠的时钟驱动器电路，其被配置为对在不同电压范围之间摆动的输入时钟信号和负载电路执行时钟信号电荷循环。 堆叠式时钟驱动器电路包括被配置为产生在不同电压范围之间摆动的输出时钟信号的堆叠驱动器电路。 负载电路包括不同半导体类型的负载网络。 每个负载网络被配置为由其中一个输出时钟信号驱动。 还描述了其它实施例。

公开(公告)号：US20200183486A1

公开(公告)日：2020-06-11

申请号：US16215780

申请日：2018-12-11

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Juan Diego Echeverri Escobar ,  Kristof Blutman ,  Sebastien Antonius Josephus Fabrie ,  Jose de Jesus Pineda de Gyvez ,  Hamed Fatemi

IPC: G06F1/3296 ,  H03K3/03

Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.

公开(公告)号：US20200073453A1

公开(公告)日：2020-03-05

申请号：US16118749

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Juan Diego Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Jurgen Geerlings ,  Hamed Fatemi

IPC: G06F1/26 ,  H02M3/137 ,  H02M3/07

Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.