公开(公告)号：US10431666B2

公开(公告)日：2019-10-01

申请号：US15935306

申请日：2018-03-26

Applicant: NXP B.V.

Inventor： Mahmoud Shehab Mohammad Al-Sa'di ,  Petrus Hubertus Cornelis Magnee

IPC: H01L29/66 ,  H01L21/266 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/36 ,  H01L29/78 ,  H01L29/167

Abstract: A semiconductor switch device and a method of making the same. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type. The method further includes implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on a gate dielectric to form a gate electrode located directly above the well region. The method further includes performing ion implantation to form a source region located in the well region on a first side of the gate, and to form a drain region located outside the well region on a second side of the gate.

公开(公告)号：US09570546B2

公开(公告)日：2017-02-14

申请号：US14852385

申请日：2015-09-11

Applicant: NXP B.V.

Inventor： Tony Vanhoucke ,  Viet Thanh Dinh ,  Petrus Hubertus Cornelis Magnee ,  Ponky Ivo ,  Dirk Klaassen ,  Mahmoud Shehab Mohammad Al-Sa'di

IPC: H01L29/06 ,  H01L29/66 ,  H03F3/21 ,  H01L29/417 ,  H01L21/324 ,  H01L29/735 ,  H01L29/08 ,  H01L29/36 ,  H01L29/737

CPC classification number: H01L29/063 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/735 ,  H01L29/7378 ,  H03F3/21

Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.

Abstract translation: 一种包括双极晶体管的半导体器件及其制造方法。 一种功率放大器，包括双极晶体管。 双极晶体管包括具有横向延伸漂移区的集电极。 还包括位于收集器上方的基座。 双极晶体管还包括位于基极上方的发射极。 双极晶体管还包括具有不同于集电极的导电类型的掺杂区域。 掺杂区域在集电极下方横向延伸以在掺杂区域和集电极之间的接触区域处形成结。 掺杂区域具有非均匀的横向掺杂分布。 在最接近双极晶体管的集电极 - 基极结的掺杂区域的一部分中，掺杂区域的掺杂水平最高。

公开(公告)号：US09431524B2

公开(公告)日：2016-08-30

申请号：US14524365

申请日：2014-10-27

Applicant: NXP B.V.

Inventor： Johannes Josephus Theodorus Marinus Donkers ,  Petrus Hubertus Cornelis Magnee ,  Blandine Duriez ,  Evelyne Gridelet ,  Hans Mertens ,  Tony Vanhoucke

IPC: H01L31/072 ,  H01L31/109 ,  H01L29/737 ,  H01L21/8249 ,  H01L29/66 ,  H01L27/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45

CPC classification number: H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/165 ,  H01L29/456 ,  H01L29/66242

Abstract: Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate (10) comprising a pair of first isolation regions (12) separated from each other by an active region (11) comprising a collector impurity said bipolar transistor; forming a base layer stack (14, 14′) over said substrate; forming a further stack of a migration layer (15) having a first migration temperature and an etch stop layer (20) over said base layer stack (14); forming a base contact layer (16) having a second migration temperature over the further stack, the second migration temperature being higher than the first migration temperature; etching an emitter window (28) in the base contact layer over the active region, said etching step terminating at the etch stop layer; at least partially removing the etch stop layer, thereby forming cavities (29) extending from the emitter window in between the base contact layer and the redistribution layer; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. An IC comprising such a bipolar transistor is also disclosed.

Abstract translation: 公开了一种制造包括双极晶体管的集成电路的方法，所述方法包括提供包括一对第一隔离区（12）的衬底（10），所述第一隔离区（12）通过包含集电极杂质的有源区（11）彼此分离，所述有源区 晶体管 在所述衬底上形成基层叠层（14,14'）; 在所述基层堆叠（14）上方形成具有第一迁移温度和蚀刻停止层（20）的迁移层（15）的另一叠层; 形成具有超过另一堆叠的第二迁移温度的基底接触层（16），所述第二迁移温度高于所述第一迁移温度; 在所述有源区上蚀刻所述基极接触层中的发射极窗口（28），所述蚀刻步骤终止于所述蚀刻停止层; 至少部分地去除所述蚀刻停止层，从而形成从所述基底接触层和所述再分布层之间的所述发射窗延伸的空腔（29） 并在氢气氛中将所得结构暴露于第一迁移温度，由此用迁移层材料填充空腔。 还公开了包括这种双极晶体管的IC。

公开(公告)号：US20160049461A1

公开(公告)日：2016-02-18

申请号：US14925205

申请日：2015-10-28

Applicant: NXP B.V.

Inventor： Petrus Hubertus Cornelis Magnee ,  Patrick Sebel

IPC: H01L49/02 ,  H01L21/31 ,  H01L23/538 ,  H01L21/3213 ,  H01L27/06 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L28/60 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/7687 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/5223 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5384 ,  H01L23/5386 ,  H01L27/0629 ,  H01L28/40 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

Abstract: There is disclosed a metal-insulator-metal, MIM, capacitor. The MIM capacitor comprises a MIM stack formed within an interconnect metal layer. The interconnect metal layer is utilised as an electrical connection to a metal layer of the MIM stack.

Abstract translation: 公开了一种金属绝缘体金属，MIM，电容器。 MIM电容器包括形成在互连金属层内的MIM堆叠。 互连金属层用作与MIM堆叠的金属层的电连接。

公开(公告)号：US08946042B2

公开(公告)日：2015-02-03

申请号：US14177880

申请日：2014-02-11

Applicant: NXP B.V.

Inventor： Evelyne Gridelet ,  Johannes Josephus Theodorus Marinus Donkers ,  Tony Vanhoucke ,  Petrus Hubertus Cornelis Magnee ,  Hans Mertens ,  Blandine Duriez

IPC: H01L29/72 ,  H01L29/732 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/732 ,  H01L29/66242 ,  H01L29/7378

Abstract: Disclosed is a method of manufacturing a bipolar transistor, comprising providing a substrate (10) comprising a first isolation region (12) separated from a second isolation region by an active region (11) comprising a collector impurity; forming a layer stack over said substrate, said layer stack comprising a base layer (14, 14′), a silicon capping layer (15) over said base layer and a silicon-germanium (SiGe) base contact layer (40) over said silicon capping layer; etching the SiGe base contact layer to form an emitter window (50) over the collector impurity, wherein the silicon emitter cap layer is used as etch stop layer; forming sidewall spacers (22) in the emitter window; and filling the emitter window with an emitter material (24). A bipolar transistor manufactured in accordance with this method and an IC comprising one or more of such bipolar transistors are also disclosed.

Abstract translation: 公开了一种制造双极晶体管的方法，包括提供包括通过包括集电极杂质的有源区（11）与第二隔离区分离的第一隔离区（12）的衬底（10） 在所述衬底上形成层堆叠，所述层堆叠包括在所述基底层上方的基底层（14,14'），硅覆盖层（15）和位于所述硅上的硅 - 锗（SiGe）基底接触层（40） 盖层; 蚀刻SiGe基极接触层以在集电极杂质上形成发射极窗口（50），其中硅发射极盖层用作蚀刻停止层; 在发射器窗口中形成侧壁间隔物（22）; 以及用发射体材料（24）填充发射器窗口。 还公开了根据该方法制造的双极晶体管和包括一个或多个这样的双极晶体管的IC。

公开(公告)号：US20140327110A1

公开(公告)日：2014-11-06

申请号：US14259550

申请日：2014-04-23

Applicant: NXP B.V.

Inventor： Evelyne Gridelet ,  Johannes Donkers ,  Petrus Hubertus Cornelis Magnee ,  Viet Dinh ,  Tony Vanhoucke

IPC: H01L29/732 ,  H01L29/66

CPC classification number: H01L29/732 ,  H01L29/407 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/7378

Abstract: Consistent with an example embodiment, a bipolar transistor comprises an emitter region vertically separated from a collector region in a substrate by a base region. The bipolar transistor further comprises a field plate electrically connected to the emitter region; the field plate extends from the emitter region along the base region into the collector region and the field plate is laterally electrically insulated from the base region and the collector region by a spacer. The spacer comprises an electrically isolating material that includes a silicon nitride layer and is vertically electrically isolated from the substrate by a further electrically isolating material.

Abstract translation: 与示例实施例一致，双极晶体管包括通过基极区域与衬底中的集电极区域垂直分离的发射极区域。 双极晶体管还包括电连接到发射极区的场板; 场板沿着基极区域从发射极区域延伸到集电极区域，并且场板通过间隔物与基极区域和集电极区域横向电绝缘。 间隔物包括电绝缘材料，其包括氮化硅层，并通过另外的电绝缘材料与衬底垂直电隔离。