公开(公告)号：US20120309145A1

公开(公告)日：2012-12-06

申请号：US13417787

申请日：2012-03-12

申请人： Moon-kyun Song ,  Ha-jin Lim ,  Moon-han Park ,  Jin-ho Do

发明人： Moon-kyun Song ,  Ha-jin Lim ,  Moon-han Park ,  Jin-ho Do

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823807

摘要： Methods of manufacturing semiconductor devices include providing a substrate including a NMOS region and a PMOS region, implanting fluorine ions into an upper surface of the substrate, forming a first gate electrode of the NMOS region and a second gate electrode of the PMOS region on the substrate, forming a source region and a drain region in portions of the substrate, which are adjacent to two lateral surfaces of the first gate electrode and the second gate electrode, respectively, and performing a high-pressure heat-treatment process on an upper surface of the substrate by using non-oxidizing gas.

摘要翻译： 制造半导体器件的方法包括提供包括NMOS区域和PMOS区域的衬底，将氟离子注入到衬底的上表面中，形成NMOS区域的第一栅极电极和衬底上的PMOS区域的第二栅极电极 在所述基板的与所述第一栅电极和所述第二栅电极的两个侧面相邻的部分分别形成源极区域和漏极区域，并在所述第一栅极电极和所述第二栅极电极的上表面上进行高压热处理工序 通过使用非氧化气体的基板。

公开(公告)号：US20100233864A1

公开(公告)日：2010-09-16

申请号：US12656842

申请日：2010-02-17

申请人： Ho Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Myung-sun Kim ,  Hoi-sung Chung

发明人： Ho Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Myung-sun Kim ,  Hoi-sung Chung

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/76825 ,  H01L21/76829 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： Methods of fabricating a semiconductor device are provided, the methods include forming a gate stack on a substrate, forming an insulation layer on the substrate to cover the gate stack, forming a spacer at both side walls of the gate stack by etching the insulation layer, and ion implanting impurities in the spacer or the insulation layer.

摘要翻译： 提供了制造半导体器件的方法，所述方法包括在衬底上形成栅极堆叠，在衬底上形成绝缘层以覆盖栅极堆叠，通过蚀刻绝缘层在栅极堆叠的两个侧壁处形成间隔物， 以及在间隔物或绝缘层中离子注入杂质。

公开(公告)号：US20090020845A1

公开(公告)日：2009-01-22

申请号：US12106671

申请日：2008-04-21

申请人： Dong-suk Shin ,  Moon-han Park ,  Joo-won Lee ,  Jae-yoon Yoo ,  Tae-gyun Kim

发明人： Dong-suk Shin ,  Moon-han Park ,  Joo-won Lee ,  Jae-yoon Yoo ,  Tae-gyun Kim

IPC分类号： H01L21/762 ,  H01L23/00

CPC分类号： H01L21/3105 ,  H01L21/31155 ,  H01L21/76232

摘要： A semiconductor device includes a substrate having a trench, a sidewall liner that covers inner walls of the trench, a doped oxide film liner on the sidewall liner in the trench, and a gap-fill insulating film that buries the trench on the doped oxide film liner. In order to form the doped oxide film liner, an oxide film liner is doped with a dopant under a plasma atmosphere. Related methods are also disclosed.

摘要翻译： 半导体器件包括具有沟槽的衬底，覆盖沟槽的内壁的侧壁衬套，沟槽中的侧壁衬里上的掺杂氧化膜衬垫，以及将掺杂氧化物膜上的沟槽埋入的间隙填充绝缘膜 衬垫。 为了形成掺杂的氧化物膜衬垫，在等离子体气氛下，掺杂有氧化物膜衬垫。 还公开了相关方法。

公开(公告)号：US20060183296A1

公开(公告)日：2006-08-17

申请号：US11398536

申请日：2006-04-06

申请人： Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

发明人： Jae-yoon Yoo ,  Moon-han Park ,  Dong-ho Ahn ,  Sug-hun Hong ,  Kyung-won Park ,  Jeong-soo Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： An isolation method for a semiconductor device where an insulating mask layer is formed on desired regions of a semiconductor substrate. A trench is formed to a desired depth in the semiconductor substrate using the insulating mask layer as a mask. An oxide layer is formed on the insulating mask layer and on the sidewall of the trench. A trench liner layer is formed on the oxide layer. An insulating filler layer is formed in the trench in the semiconductor substrate, on which the trench liner layer is formed, so as to fill the trench. The insulating mask layer is removed. According to the isolation method for a semiconductor device, it is possible to reduce dents from occurring along the edge of the trench, reduce a bird's beak type oxide layer from occurring at an interface between the insulating mask layers, decrease the leakage current, or improve the electrical characteristics, such as threshold voltage.

公开(公告)号：US07033895B2

公开(公告)日：2006-04-25

申请号：US10823420

申请日：2004-04-13

申请人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

发明人： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

摘要： In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

摘要翻译： 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。

公开(公告)号：US06835621B2

公开(公告)日：2004-12-28

申请号：US10455676

申请日：2003-06-05

申请人： Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

发明人： Jae-yoon Yoo ,  Moon-han Park ,  Dae-jin Kwon

IPC分类号： H01L218247

CPC分类号： H01L27/11568 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02326 ,  H01L21/28282 ,  H01L21/3144 ,  H01L21/31612 ,  H01L21/32105 ,  H01L27/115 ,  H01L29/66833

摘要： In a method of fabricating a non-volatile memory device with a silicon-oxide-nitride-oxide-silicon (SONOS) structure, a silicon nitride layer, which is a charge trapping layer, and a polysilicon layer, which is a control gate electrode, are electrically isolated from one another in the resulting structure. According to the method, a silicon oxide layer as a tunneling layer and a silicon nitride layer pattern as a charge trapping layer are formed on a semiconductor substrate; an oxidation process is performed to form a silicon nitride oxide layer, as a blocking layer, at top and sides of the silicon nitride layer pattern and to form a gate insulating layer at an exposed portion of the semiconductor substrate; and a control gate electrode is formed on the silicon nitride oxide layer and the gate insulating layer.

摘要翻译： 在制造具有氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的非易失性存储器件的方法中，作为电荷俘获层的氮化硅层和作为控制栅电极的多晶硅层 在所得结构中彼此电隔离。 根据该方法，在半导体衬底上形成作为隧穿层的氧化硅层和作为电荷俘获层的氮化硅层图案; 进行氧化处理以在氮化硅层图案的顶部和侧面形成氮化硅氧化物层作为阻挡层，并在半导体衬底的暴露部分形成栅极绝缘层; 并且在氮氧化硅层和栅极绝缘层上形成控制栅电极。

公开(公告)号：US06537914B1

公开(公告)日：2003-03-25

申请号：US09570225

申请日：2000-05-12

申请人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee ,  Jung-yup Kim ,  Chang-ki Hong ,  Ho-kyu Kang

发明人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee ,  Jung-yup Kim ,  Chang-ki Hong ,  Ho-kyu Kang

IPC分类号： H01L21302

CPC分类号： C09G1/02 ,  C09K3/1463 ,  H01L21/31053 ,  H01L21/76224

摘要： Trench isolation methods for integrated circuits may reduce irregularities in the formation of an isolation layer through use of a high selectivity chemical-mechanical polishing (CMP) operation. In particular, a substrate surface is etched to form a trench. An insulation layer is then formed on the substrate surface and in the trench. The insulation layer is chemical-mechanical polished using a slurry that includes a CeO2 group abrasive to form an isolation layer in the trench. The CMP selectivity ratio of a slurry that includes a CeO2 group abrasive may be sufficient to allow the substrate surface to be used as a CMP stop. As a result, a more consistent level of polishing may be maintained over the substrate surface, which may result in a more uniform thickness in the isolation layer.

摘要翻译： 用于集成电路的沟槽隔离方法可以通过使用高选择性化学机械抛光（CMP）操作来减少形成隔离层的不规则性。 特别地，蚀刻衬底表面以形成沟槽。 然后在衬底表面和沟槽中形成绝缘层。 绝缘层使用包含CeO 2基团研磨剂的浆料进行化学机械抛光，以在沟槽中形成隔离层。 包括CeO 2基研磨剂的浆料的CMP选择比可能足以使基板表面用作CMP停止。 结果，可以在衬底表面上保持更一致的抛光水平，这可能导致隔离层中更均匀的厚度。

公开(公告)号：US06331469B1

公开(公告)日：2001-12-18

申请号：US09684822

申请日：2000-10-10

申请人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

发明人： Tai-su Park ,  Moon-han Park ,  Kyung-won Park ,  Han-sin Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76235

摘要： A trench isolation structure which prevents a hump phenomenon and an inverse narrow width effect of transistors by rounding the top edges of a trench and increasing the amount of oxidation at the top edges of a trench, a semiconductor device having the trench isolation structure, and a trench isolation method are provided. In this trench isolation method, a trench is formed in non-active regions of a semiconductor substrate. An inner wall oxide film having a thickness of 10 to 150 Å is formed on the inner wall of the trench. A liner is formed on the surface of the inner wall oxide film. The trench is filled with a dielectric film. Part of the liner is etched so that the top ends of the silicon nitride liner are recessed from the surface of the semiconductor substrate.

摘要翻译： 一种沟槽隔离结构，其通过对沟槽的顶部边缘进行舍入并增加在沟槽的顶部边缘处的氧化量，具有沟槽隔离结构的半导体器件和防止沟槽隔离结构的半导体器件，从而防止晶体管的隆起现象和反向窄宽度效应 提供沟槽隔离方法。 在这种沟槽隔离方法中，在半导体衬底的非有源区中形成沟槽。 在沟槽的内壁上形成厚度为10至150埃的内壁氧化膜。 在内壁氧化膜的表面上形成衬垫。 沟槽填充有电介质膜。 蚀刻衬垫的一部分，使得氮化硅衬垫的顶端从半导体衬底的表面凹陷。

公开(公告)号：US6037237A

公开(公告)日：2000-03-14

申请号：US22513

申请日：1998-02-12

申请人： Moon-han Park ,  Sug-hun Hong ,  Yu-gyun Shin

发明人： Moon-han Park ,  Sug-hun Hong ,  Yu-gyun Shin

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76232

摘要： A multilayer oxide film, including at least two oxide layers having differing stress characteristics, is used in a trench isolation method. Preferably, at least a first one of the oxide layers has tensile stress characteristics and at least a second one of the oxide layers has compressive stress characteristics. Thus, during densification, the overall stress can be reduced. The multilayer film is preferably formed by sequentially stacking first and second oxide films which have opposite stress characteristics. In one example, the first oxide film is a tetra-ethyl-orthosilicate (TEOS)-O.sub.3 based chemical vapor deposition (CVD) oxide film and the second oxide film is selected from the group consisting of TEOS-based plasma-enhanced CVD (PECVD) oxide film, an SiH.sub.4 based PECVD oxide film and a high density plasma (HDP) oxide film. In another embodiment, the first oxide film is an HDP oxide film and the second film is a TEOS-O.sub.3 based CVD oxide film. Accordingly, integrated circuits with reduced stress may be fabricated, thereby allowing increased performance of the integrated circuits.

摘要翻译： 在沟槽隔离方法中使用包括具有不同应力特性的至少两个氧化物层的多层氧化物膜。 优选地，氧化物层中的至少第一层具有拉伸应力特性，并且至少第二个氧化物层具有压应力特性。 因此，在致密化期间，可以降低整体应力。 多层膜优选通过顺序堆叠具有相反应力特性的第一和第二氧化膜形成。 在一个实例中，第一氧化物膜是基于四乙基原硅酸盐（TEOS）-O 3的化学气相沉积（CVD）氧化物膜，第二氧化物膜选自基于TEOS的等离子体增强CVD（PECVD） ）氧化物膜，基于SiH 4的PECVD氧化物膜和高密度等离子体（HDP）氧化物膜。 在另一实施例中，第一氧化膜是HDP氧化物膜，第二膜是基于TEOS-O 3的CVD氧化物膜。 因此，可以制造具有减小的应力的集成电路，从而允许集成电路的性能提高。