公开(公告)号：US07453244B1

公开(公告)日：2008-11-18

申请号：US11699198

申请日：2007-01-29

申请人： James T. Doyle

发明人： James T. Doyle

IPC分类号： G05F1/56

CPC分类号： G05F1/575

摘要： A hard saturation mode of operation can be avoided in an LDO regulator by providing an additional feedback control loop. The additional control loop cooperates with the LDO regulator's amplifier stage and output stage to maintain at least a minimum desired voltage drop across the output stage from the power supply to the load.

摘要翻译： 通过提供额外的反馈控制回路，可以在LDO稳压器中避免硬饱和工作模式。 附加的控制回路与LDO调节器的放大器级和输出级配合，以在输出级上至少保持从电源到负载的最小期望电压降。

公开(公告)号：US07436243B1

公开(公告)日：2008-10-14

申请号：US11065431

申请日：2005-02-24

申请人： James T. Doyle ,  Dae Woon Kang

发明人： James T. Doyle ,  Dae Woon Kang

IPC分类号： G05F3/16 ,  G05F1/10

CPC分类号： G05F3/30 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

摘要： On-chip AC noise suppression is provided for a target circuit within an integrated circuit chip. A power supply line filter is provided in the power supply line that feeds the target circuit. The filter includes a polysilicon resistor formed over a charged substrate well, with a dielectric material interposed between the well and the resistor. This decreases capacitive coupling between the substrate and the resistor, thereby suppressing AC noise that is injected via the substrate. For an on-chip bandgap reference circuit, AC noise suppression can be achieved by providing matched AC impedances in the PTAT and inverse PTAT branches of the circuit. This technique exploits the common-mode rejection capability of the error amplifier within the bandgap reference circuit. Also, the inputs of the error amplifier can be capacitively coupled together to exploit the amplifier's common-mode rejection capability for the suppression of AC noise that is injected at the amplifier inputs.

摘要翻译： 为集成电路芯片内的目标电路提供片上AC噪声抑制。 在馈电目标电路的电源线上设置电源线滤波器。 滤波器包括形成在带电衬底阱上的多晶硅电阻器，介电材料置于阱和电阻器之间。 这降低了衬底和电阻器之间的电容耦合，从而抑制了通过衬底注入的AC噪声。 对于片上带隙参考电路，可以通过在电路的PTAT和反向PTAT分支中提供匹配的交流阻抗来实现交流噪声抑制。 该技术利用带隙参考电路内的误差放大器的共模抑制能力。 此外，误差放大器的输入可以电容耦合在一起以利用放大器的共模抑制能力来抑制在放大器输入处注入的AC噪声。

公开(公告)号：US06323674B1

公开(公告)日：2001-11-27

申请号：US09515270

申请日：2000-02-29

申请人： Udbhava A. Shrivastava ,  James T. Doyle ,  Edward J. Bawolek

发明人： Udbhava A. Shrivastava ,  James T. Doyle ,  Edward J. Bawolek

IPC分类号： H03K19003

CPC分类号： H04L25/0298

摘要： A system includes a transmission line, a driver, a load, a compensation capacitor and a compensation resistor. An output terminal of the driver is coupled to one end of the transmission line, and the load is coupled to the other end of the transmission line. The compensation capacitor is coupled in parallel with the output terminal of the driver, and the compensation resistor is coupled in series between the other end of the transmission line and the load.

摘要翻译： 系统包括传输线，驱动器，负载，补偿电容器和补偿电阻器。 驱动器的输出端耦合到传输线的一端，并且负载耦合到传输线的另一端。 补偿电容器与驱动器的输出端并联，补偿电阻串联在传输线的另一端和负载之间。

公开(公告)号：US06009124A

公开(公告)日：1999-12-28

申请号：US934789

申请日：1997-09-22

申请人： James P. Smith ,  James T. Doyle

发明人： James P. Smith ,  James T. Doyle

IPC分类号： H01Q1/24 ,  H01Q3/26 ,  H04B7/08 ,  H04B7/02 ,  H04L1/02

CPC分类号： H04B7/0851 ,  H01Q1/246 ,  H01Q3/2605 ,  H04L1/0016

摘要： A high data rate communication system that employs an adaptive sectored antenna is disclosed. The high data rate communication system includes an antenna subsystem for receiving and transmitting data. The antenna subsystem is adapted to be spatially steered. A radio frequency transceiver that is coupled to the antenna subsystem and that selectively generates a bit error rate (BER) signal and a receive signal strength indication (RSSI) signal based upon a received antenna training sequence is also provided. The system also includes a beam steering state machine that is coupled to the radio frequency transceiver and that selectively generates a BER.sub.-- PASS signal and an RSSI.sub.-- PASS signal based upon whether the BER signal is in a first logical relationship with a predetermined BER signal and the RSSI signal is in a second logical relationship with a predetermined RSSI signal. An antenna controller is coupled to the antenna subsystem and the beam steering state machine and selectively generates antenna control signals to spatially steer the antenna subsystem based upon the BER.sub.-- PASS signal and the RSSI.sub.-- PASS signal.

摘要翻译： 公开了采用自适应扇形天线的高数据速率通信系统。 高数据速率通信系统包括用于接收和发送数据的天线子系统。 天线子系统适于空间转向。 还提供耦合到天线子系统并且基于接收到的天线训练序列选择性地生成误码率（BER）信号和接收信号强度指示（RSSI）信号的射频收发器。 该系统还包括耦合到射频收发器的波束导向状态机，并且基于BER信号是否与预定的BER信号处于第一逻辑关系，并选择性地产生BER-通过信号和RSSI-PASS信号，以及 RSSI信号与预定的RSSI信号处于第二逻辑关系。 天线控制器耦合到天线子系统和波束导向状态机，并且基于BER-通过信号和RSSI-PASS信号选择性地产生天线控制信号以空间转向天线子系统。

公开(公告)号：US5694439A

公开(公告)日：1997-12-02

申请号：US408270

申请日：1995-03-21

申请人： James T. Doyle ,  Carl F. Liepold

发明人： James T. Doyle ,  Carl F. Liepold

IPC分类号： H03F3/45 ,  H03H7/01 ,  H03H11/04 ,  H04L5/16 ,  H04L25/03 ,  H04B1/10

CPC分类号： H03H7/1766 ,  H03F3/45085 ,  H03H11/045 ,  H03H7/0115 ,  H04L25/03343 ,  H04L5/16 ,  H03F2203/45371 ,  H03F2203/45574 ,  H03F2203/45612

摘要： The present invention provides a bi-directional low pass filtering method and apparatus for attenuating out-of-baseband components of data transmitted from an encoder to a decoder over a transmission medium. In one embodiment of the present invention, the bi-directional low pass filtering apparatus includes a Chebyshev filter that has a first phase response. This Chebyshev filter is coupled to a phase correction circuit, which has a second phase response. This second phase response of the phase correction circuit is designed to oppose the first phase response in order to offset variations in group delay in the data due to the Chebyshev filter.

摘要翻译： 本发明提供一种双向低通滤波方法和装置，用于通过传输介质衰减从编码器发送到解码器的数据的基带外分量。 在本发明的一个实施例中，双向低通滤波装置包括具有第一相位响应的切比雪夫滤波器。 该切比雪夫滤波器耦合到具有第二相位响应的相位校正电路。 相位校正电路的第二相位响应被设计为与第一相位响应相反，以便抵消由切比雪夫滤波器引起的数据中组延迟的变化。

公开(公告)号：US5202590A

公开(公告)日：1993-04-13

申请号：US788491

申请日：1991-11-06

申请人： Carl F. Liepold ,  James T. Doyle

发明人： Carl F. Liepold ,  James T. Doyle

IPC分类号： H03F1/30 ,  H03K5/003 ,  H03K5/08

CPC分类号： H03K5/003 ,  H03F1/301 ,  H03K5/086

摘要： A subthreshold sense circuit for clamping an injected current at the input pins of an integrated circuit device before the injected current causes the voltage at the input pins to exceed the supply voltage by more than a diode's ON voltage. The subthreshold sense circuit is driven to operate in the linear region of the FETs. The subthreshold sense circuit of the present invention comprises level shifters, a subthreshold current source, a reference voltage generator, a subthreshold comparator, and a clamping circuit. The subthreshold current source generates a reference drain current to drive the sense circuit of the present invention in the linear region. A level shifter is connected to an input pin to shift the voltage level of the input pin by a subthreshold voltage level. The reference voltage generator provides a reference voltage to be compared with the subthreshold-shifted input voltage. The subthreshold comparator compares the subthreshold-shifted input voltage with the reference voltage level such that when the subthreshold-shifted input voltage from the input pin exceeds the reference voltage level, the subthreshold comparator will turn on. The clamping circuit is activated by the subthreshold comparator to clamp the input pin to less than one V.sub.D (ON) drop over the supply voltage by sinking the injected current at the input pin when the subthreshold comparator is turned on.

摘要翻译： 在注入电流之前，用于钳位在集成电路器件的输入引脚处的注入电流的亚阈值感测电路使得​​输入引脚处的电压超过电源电压超过二极管的导通电压。 亚阈值检测电路被驱动以在FET的线性区域中工作。 本发明的亚阈值检测电路包括电平移位器，亚阈值电流源，参考电压发生器，亚阈值比较器和钳位电路。 亚阈值电流源产生参考漏极电流，以在线性区域中驱动本发明的感测电路。 电平移位器连接到输入引脚，以将输入引脚的电压电平移位亚阈值电压电平。 参考电压发生器提供与亚阈值移位输入电压进行比较的参考电压。 亚阈值比较器将亚阈值移位输入电压与参考电压电平进行比较，使得当来自输入引脚的亚阈值移位输入电压超过参考电压电平时，子阈值比较器将导通。 钳位电路由次阈值比较器激活，通过在亚阈值比较器导通时将输入引脚上的注入电流吸收，将输入引脚钳位在电源电压下的一个VD（ON）下降。

公开(公告)号：US4835487A

公开(公告)日：1989-05-30

申请号：US181607

申请日：1988-04-14

申请人： James T. Doyle ,  Bart R. McDaniel

发明人： James T. Doyle ,  Bart R. McDaniel

IPC分类号： H03F3/34 ,  H03F3/345 ,  H03F3/347

CPC分类号： H03F3/345

摘要： A voltage to current converter circuit manufactured with a MOS process generates a linear reference current over a wide bandwidth and operates with an input signal that varies to either supply rail. A voltage divider network scales an input voltage for conversion to a linear current by a cascode current mirror and a gain resistor. The value of the gain resistor determines the transconductance of the conversion from voltage to current. A second current mirror provides feedback to keep the reference current accurate. An output stage makes available high impedance source and sink current output terminals wherein a source current and a sink current relative to the reference current are provided. Several voltage to current converter circuits may be coupled together to provide a addition, subtraction, multiplication, and other circuit and system functions.

公开(公告)号：US4717836A

公开(公告)日：1988-01-05

申请号：US825863

申请日：1986-02-04

申请人： James T. Doyle

发明人： James T. Doyle

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03F1/30 ,  H03F3/345 ,  H03K19/003 ,  H03K19/0185 ,  H03K17/14

CPC分类号： H01L27/0211 ,  H03F1/301 ,  H03F3/345 ,  H03K19/00384 ,  H03K19/018507 ,  H03K19/018521 ,  H01L2924/0002

摘要： A CMOS input level shifting circuit includes a temperature-compensating N-channel field effect transistor structure wherein a resistance in series with the source region includes an extension of a lightly doped P-type region in which the source and drain regions are diffused. This structure produces a temperature-compensating variation in the drain current proportional to the square of the series resistance without requiring modification of standard processes for manufacturing CMOS integrated circuits. The relatively large, temperature-dependent variation of the series resistance produces a corresponding temperature-dependent variation in the drain current that effectively temperature-compensates the switching point of the CMOS input level shifting circuit.

摘要翻译： CMOS输入电平移位电路包括温度补偿N沟道场效应晶体管结构，其中与源极区串联的电阻包括其中源区和漏区扩散的轻掺杂P型区的延伸。 该结构产生与串联电阻的平方成比例的漏极电流的温度补偿变化，而不需要修改用于制造CMOS集成电路的标准工艺。 串联电阻的相对大的温度依赖性变化产生相应的温度依赖的漏极电流变化，其有效地温度补偿CMOS输入电平移位电路的开关点。

公开(公告)号：US4646427A

公开(公告)日：1987-03-03

申请号：US625751

申请日：1984-06-28

申请人： James T. Doyle

发明人： James T. Doyle

IPC分类号： G11C17/08 ,  G11C17/16 ,  H01L21/326 ,  H01L21/768 ,  H01L29/04 ,  H01L29/866

CPC分类号： H01L29/04 ,  G11C17/08 ,  G11C17/16 ,  H01L21/326 ,  H01L21/76888 ,  H01L29/866 ,  Y10S148/013 ,  Y10S148/018 ,  Y10S148/055 ,  Y10S148/122 ,  Y10S148/154 ,  Y10S148/174 ,  Y10S438/983

摘要： In a method of electrically altering the characteristics of a semiconductor device, a lateral polysilicon zener diode's zener knee voltage may be shifted either to a higher or lower voltage. An electrical potential may be applied in the forward direction to shift the zener knee to a higher voltage level. An electrical potential may be applied in the reverse bias direction to shift the zener knee to a lower voltage. In the limit, the zener may be changed into a forward diode of reverse polarity with respect to the original zener. The electrical potential used should be of appropriate magnitude to melt the polysilicon without damage to the zener's terminals. This induces migration of the impurities causing a rediffusion of impurities thereby altering the characteristics of the diode. This method may be used to program a PROM by either converting the zener to a diode or not to program each binary bit. The device may also be used as an analog memory element by setting an entire word equal to a predetermined zener knee voltage.

摘要翻译： 在电子改变半导体器件的特性的方法中，横向多晶硅齐纳二极管的齐纳拐点电压可以移动到更高或更低的电压。 可以向前方向施加电位以将齐纳膝盖移动到更高的电压水平。 可以在反向偏置方向上施加电位以将齐纳膝盖移动到较低的电压。 在极限情况下，可以将齐纳二极管变成相对于原始齐纳二极管的正极二极管。 所使用的电位应该是适当的大小，以熔化多晶硅而不损坏齐纳尔的端子。 这引起杂质的迁移，导致杂质的再扩散，从而改变二极管的特性。 该方法可用于通过将齐纳二极管转换为二极管来编程PROM来对每个二进制位进行编程。 该设备也可以通过设置等于预定的齐纳膝盖电压的整个字来用作模拟存储器元件。

公开(公告)号：US07852252B2

公开(公告)日：2010-12-14

申请号：US12347081

申请日：2008-12-31

申请人： Fuding Ge ,  Brent D. Thomas ,  Malay Trivedi ,  James T. Doyle

发明人： Fuding Ge ,  Brent D. Thomas ,  Malay Trivedi ,  James T. Doyle

IPC分类号： H03M1/12

CPC分类号： H03F3/005 ,  H03F3/45475

摘要： Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth.

摘要翻译： 将单端模拟信号放大并转换为差分信号并将差分信号转换为数字值的方法和系统，包括对多个窗口化的单端模拟误差信号进行时间复用，放大时间差 多路复用模拟信号，对相应的放大差分信号和反相放大差分信号进行采样，对共模进行放大和中心采样，并以相应的方式将相应的放大差分信号转换为数字值。 可以实施偏置可调特征以控制带宽，并且时钟速率可以是可调节的以对应于带宽。