公开(公告)号：US20200304136A1

公开(公告)日：2020-09-24

申请号：US16896494

申请日：2020-06-09

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H03M1/46 ,  H03M1/36 ,  H03M1/18

Abstract: An AD conversion circuit includes a comparison circuit, a first DA conversion circuit including a plurality of resistance elements, and a first voltage output circuit. A comparator of the comparison circuit outputs a signal that represents a result of comparing a first voltage of a first input terminal with a second voltage of a second input terminal, A first combined resistance value of the first DA conversion circuit and the first voltage output circuit seen from a second terminal of the first capacitance element is a first value when the first capacitance element holds a first signal. The first combined resistance value is a second value when the comparator compares the first voltage with the second voltage. The first value is less than the second value.

公开(公告)号：US20190110012A1

公开(公告)日：2019-04-11

申请号：US16214772

申请日：2018-12-10

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/378 ,  H04N5/374 ,  H03M1/12

Abstract: An analog-to digital (AD) conversion circuit includes a digital-to-analog (DA) conversion circuit, an arithmetic circuit, and a comparison circuit. The DA conversion circuit generates a first reference current signal. The arithmetic circuit is electrically connected to the DA conversion circuit and generates a comparison current signal by adding the first reference current signal to a first current signal generated in accordance with a first voltage signal or subtracting the first reference current signal from the first current signal. The comparison circuit is electrically connected to the arithmetic circuit and outputs digital data based on a result of comparing a second current signal according to a second voltage signal with the comparison current signal.

公开(公告)号：US20180146152A1

公开(公告)日：2018-05-24

申请号：US15876494

申请日：2018-01-22

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/374 ,  H04N5/225 ,  H04N5/378

CPC classification number: H04N5/374 ,  A61B1/045 ,  A61B1/051 ,  A61B1/0669 ,  A61B1/07 ,  G02B23/2446 ,  G02B23/2469 ,  H04N5/2256 ,  H04N5/361 ,  H04N5/378 ,  H04N2005/2255

Abstract: An imaging device includes a plurality of pixels, a reference current generation circuit, a differential current generation circuit, a reference voltage generation circuit, a conversion circuit, and an output circuit. The differential current generation circuit generates a differential current according to a difference between a pixel current and a reference current. The conversion circuit converts the differential current into an output voltage on the basis of a first reference voltage. A second reference voltage is higher than the tint reference voltage when the output voltage at the time of resetting of the pixels is higher than the output voltage at the time of exposure of the pixels. The second reference voltage is lower than the first reference voltage when the output voltage at the time of resetting of the pixels is lower than the output voltage at the time of exposure of the pixels.

公开(公告)号：US09967491B2

公开(公告)日：2018-05-08

申请号：US15435614

申请日：2017-02-17

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/3745 ,  H01L27/146 ,  H04N5/357

CPC classification number: H04N5/3745 ,  H01L27/14614 ,  H01L27/14636 ,  H01L27/14643 ,  H04N5/3577 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/378

Abstract: A first voltage line supplies a constant first voltage in column circuits of an imaging device. A second voltage line supplies a second voltage that is lower than the first voltage and is constant. A third voltage line supplies a constant third voltage. A fourth voltage line supplies a fourth voltage that is lower than the third voltage and is constant. The first voltage line is electrically connected to a drain of an NMOS transistor, and the third voltage line is electrically connected to a gate of the NMOS transistor. The second voltage line is electrically connected to a drain of a PMOS transistor, and the fourth voltage line is electrically connected to a gate of the PMOS transistor.

公开(公告)号：US09497359B2

公开(公告)日：2016-11-15

申请号：US14699242

申请日：2015-04-29

Applicant: OLYMPUS CORPORATION

Inventor： Susumu Yamazaki ,  Yoshio Hagihara

IPC: H04N5/335 ,  H04N5/217 ,  H04N5/225 ,  H04N5/357 ,  H04N5/3745

CPC classification number: H04N5/217 ,  H04N5/2173 ,  H04N5/225 ,  H04N5/2253 ,  H04N5/2256 ,  H04N5/335 ,  H04N5/357 ,  H04N5/3575 ,  H04N5/3698 ,  H04N5/37452 ,  H04N5/37457 ,  H04N2005/2255

Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion sections configured to generate a signal charge according to an amount of an incident light and disposed in a matrix, a first accumulation section configured to accumulate the signal charge, a first transfer section configured to transfer the signal charge from the photoelectric conversion sections to the first accumulation section, a second accumulation section configured to accumulate the signal charge accumulated in the first accumulation section, a second transfer section configured to transfer the signal charge accumulated in the first accumulation section to the second accumulation section, a reset section configured to reset the signal charge accumulated in the second accumulation section, an output section configured to output a signal according to the signal charge accumulated in the second accumulation section, and first and second control sections configured to control each section for every row or column.

Abstract translation: 一种固体摄像装置，包括：多个光电转换部，被配置为根据入射光的量生成信号电荷并配置成矩阵状;第一累积部，被配置为累积信号电荷;第一转印部，被配置为 将信号电荷从光电转换部分传送到第一累积部分，第二累积部分，被配置为累积在第一累积部分中累积的信号电荷;第二传送部分，被配置为将累积在第一累积部分中的信号电荷传送到 第二累积部分，复位部分，被配置为复位在第二累积部分中累积的信号电荷;输出部分，被配置为根据累积在第二累积部分中的信号电荷输出信号;以及第一和第二控制部分， 部分为每一行 或列。

公开(公告)号：US09462204B2

公开(公告)日：2016-10-04

申请号：US14817821

申请日：2015-08-04

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/3745 ,  H03M1/08 ,  H04N5/376 ,  H04N5/63 ,  H04N5/363 ,  H04N5/378 ,  H03M1/12 ,  H03M1/56

CPC classification number: H04N5/3745 ,  H03M1/08 ,  H03M1/123 ,  H03M1/56 ,  H04N5/363 ,  H04N5/37455 ,  H04N5/3765 ,  H04N5/378 ,  H04N5/63

Abstract: An imaging device includes: an imaging section in which a plurality of unit pixels having a photoelectric conversion element are arranged in the form of a matrix; a reference signal generating section configured to generate a reference signal that increases or decreases with a passage of time; a comparison section that includes a differential amplifier including a first input terminal electrically connected to the reference signal generating section and a second input terminal electrically connected to the unit pixels and configured to compare voltages of the first input terminal and the second input terminal and is arranged for each column or for a plurality of columns of a pixel array of the imaging section; and a measurement section configured to measure a comparison time from when the comparison section starts comparison until the comparison ends and generate data corresponding to the comparison time.

Abstract translation: 一种成像装置，包括：成像部，其中具有光电转换元件的多个单位像素以矩阵的形式排列; 参考信号产生部分，被配置为产生随着时间的推移而增加或减小的参考信号; 比较部分，其包括差分放大器，包括电连接到参考信号产生部分的第一输入端子和电连接到单位像素的第二输入端子，并且被配置为比较第一输入端子和第二输入端子的电压， 对于每个列或者用于成像部分的像素阵列的多个列; 以及测量部，被配置为测量从比较部开始比较直到比较结束的比较时间，并生成与比较时间对应的数据。

公开(公告)号：US09030588B2

公开(公告)日：2015-05-12

申请号：US13953272

申请日：2013-07-29

Applicant: Olympus Corporation

Inventor： Yoshio Hagihara

IPC: H04N5/335 ,  H04N5/3745 ,  H04N5/378

CPC classification number: H04N5/37455 ,  H04N5/378

Abstract: An imaging apparatus capable of reducing deterioration of AD conversion accuracy is provided, wherein, when performing the AD conversion on a pixel signal corresponding to a reset level, a latch control unit causes a latch circuit of a latch unit to enter an enabled state (third timing) at a first timing according to a comparison start in a comparing unit, and then causes the latch circuit of the latch unit to execute latching at a fourth timing at which a predetermined time has lapsed from a second timing according to a comparison end in the comparing unit. Further, when performing the AD conversion on the pixel signal corresponding to the signal level, the latch control unit causes the latch circuit of the latch unit to enter the enabled state at the second timing according to the comparison end in the comparing unit.

Abstract translation: 提供一种能够降低AD转换精度降低的成像装置，其中，当对与复位电平相对应的像素信号执行AD转换时，锁存器控制单元使闩锁单元的锁存电路进入使能状态（第三 定时）根据比较单元中的比较开始在第一定时，然后使得锁存单元的锁存电路在第二定时从根据比较结束的第二定时经过预定时间的第四定时执行锁存 比较单位。 此外，当对与信号电平相对应的像素信号执行AD转换时，锁存器控制单元根据比较单元中的比较结束，使闩锁单元的锁存电路在第二定时进入使能状态。

公开(公告)号：US08957953B2

公开(公告)日：2015-02-17

申请号：US13650589

申请日：2012-10-12

Applicant: Olympus Corporation

Inventor： Yoshio Hagihara

IPC: H04N5/335 ,  H04N7/18 ,  G02B23/24 ,  H04N5/3745 ,  H04N5/378 ,  H04N5/225

CPC classification number: G02B23/2484 ,  H04N5/3745 ,  H04N5/37457 ,  H04N5/378 ,  H04N2005/2255

Abstract: An imaging device and an endoscopic device can be further miniaturized. A vertical selection unit simultaneously resets charge accumulation units of a plurality of pixels, and then a horizontal selection unit sequentially selects a plurality of first pixel signals corresponding to voltages of the charge accumulation units of the plurality of pixels and inputs the first pixel signals to an output unit. Further, a vertical selection unit simultaneously transfers the signal charges generated by the charge generation units in the plurality of pixels to the charge accumulation units, and then a horizontal selection unit sequentially selects a plurality of second pixel signals corresponding to the voltages of the charge accumulation units of the plurality of pixels and inputs the second pixel signals to the output unit.

Abstract translation: 成像装置和内窥镜装置可以进一步小型化。 垂直选择单元同时复位多个像素的电荷累积单元，然后水平选择单元顺序地选择与多个像素中的电荷累积单元的电压相对应的多个第一像素信号，并将第一像素信号输入到 输出单元。 此外，垂直选择单元同时将由多个像素中的电荷产生单元生成的信号电荷同时传送到电荷累积单元，然后水平选择单元顺序地选择与电荷累积的电压对应的多个第二像素信号 多个像素的单位，并将第二像素信号输入到输出单元。

公开(公告)号：US08823575B2

公开(公告)日：2014-09-02

申请号：US14037842

申请日：2013-09-26

Applicant: Olympus Corporation

Inventor： Yoshio Hagihara

IPC: H03M1/56 ,  H03M1/34 ,  H04N5/3745

CPC classification number: H04N5/37455 ,  G04F10/005 ,  H03M1/08 ,  H03M1/123 ,  H03M1/34 ,  H03M1/56

Abstract: An AD conversion circuit may include: a reference signal generation unit generating a reference signal increasing or decreasing with passage of time; a comparison unit including a first comparison circuit and a second comparison circuit comparing an analog signal to be subjected to an AD conversion with the reference signal; a clock generation unit including a delay circuit in which a plurality of delay units are connected to one another, and outputting a first lower phase signal and a second lower phase signal based on clock signals output from each of the plurality of delay units; a latch unit including a first latch circuit latching a logical state of the first lower phase signal and a second latch circuit latching a logical state of the second lower phase signal; and a counting unit performing counting based on the second lower phase signal output from the clock generation unit.

Abstract translation: AD转换电路可以包括：参考信号生成单元，其产生随着时间的推移而增加或减小的参考信号; 比较单元，包括将要进行AD转换的模拟信号与参考信号进行比较的第一比较电路和第二比较电路; 时钟生成单元，其包括延迟电路，其中多个延迟单元彼此连接，并且基于从所述多个延迟单元中的每一个输出的时钟信号输出第一下相位信号和第二下相位信号; 锁存单元，包括锁存第一下相位信号的逻辑状态的第一锁存电路和锁存第二下相位信号的逻辑状态的第二锁存电路; 以及计数单元，基于从时钟生成单元输出的第二下相位信号进行计数。

公开(公告)号：US20140036122A1

公开(公告)日：2014-02-06

申请号：US13952947

申请日：2013-07-29

Applicant: OLYMPUS CORPORATION

Inventor： Yoshio Hagihara

IPC: H04N5/378

CPC classification number: H04N5/378

Abstract: An AD conversion circuit may include: a reference signal generation unit; a comparison unit; a clock generation unit; a latch unit; a counting unit; and an encoding unit including a detection circuit and an encoding circuit, the detection circuit performing a first detection operation of detecting logic states of n lower phase signals in a signal group that a plurality of lower phase signals latched in the latch unit are arranged in the same order as those of the signal group when the plurality of lower phase signals output from the clock generation unit are arranged to be the signal group the detection circuit outputting a state detection signal when the logic state of the n lower phase signals is detected to be a predetermined logic state in the first detection operation, the encoding circuit performing encoding based on the state detection signal output from the detection circuit.

Abstract translation: AD转换电路可以包括：参考信号生成单元; 比较单位 时钟发生单元; 闩锁单元; 计数单位 以及包括检测电路和编码电路的编码单元，所述检测电路执行检测锁存单元中锁存的多个下相位信号的信号组中n个下相位信号的逻辑状态的第一检测操作， 当从时钟发生单元输出的多个下相位信号被布置为信号组时，当检测到n个较低相位信号的逻辑状态被检测为检测电路输出状态检测信号时，与信号组相同的顺序 在第一检测操作中的预定逻辑状态，编码电路根据从检测电路输出的状态检测信号进行编码。