Semiconductor Chip, Method of Producing a Semiconductor Chip and Apparatus Having a Plurality of Semiconductor Chips

    公开(公告)号:US20200168505A1

    公开(公告)日:2020-05-28

    申请号:US16078995

    申请日:2017-06-21

    Abstract: A semiconductor chip, a method for producing a semiconductor chip and an apparatus having a plurality of semiconductor chips are disclosed. In an embodiment a chip includes a substrate and a semiconductor layer arranged at the substrate, wherein the substrate includes, at a side facing the semiconductor layer, a top side with a width B1 in a first lateral direction and, at a side opposite to the top side, a bottom side with a width B3 in the first lateral direction, wherein the substrate has a width B2 in the first lateral direction at a half height between the top side and the bottom side, and wherein the following applies to widths B1, B2 and B3: B1-B2 B3.

    Method for producing an optoelectronic semiconductor component, and optoelectronic semiconductor component

    公开(公告)号:US10516079B2

    公开(公告)日:2019-12-24

    申请号:US16006765

    申请日:2018-06-12

    Abstract: A method is specified for producing an optoelectronic semiconductor component, comprising the following steps: A) providing a structured semiconductor layer sequence (21, 22, 23) having a first semiconductor layer (21) with a base region (21c), at least one well (211), and a first cover region (21a) in the region of the well (211) facing away from the base surface (21c), an active layer (23), and a second semiconductor layer (22) on a side of the active layer (23) facing away from the first semiconductor layer (21), wherein the active layer (23) and the second semiconductor layer (22) are structured jointly in a plurality of regions (221, 231) and each region (221, 231) forms, together with the first semiconductor layer (21), an emission region (3), B) simultaneous application of a first contact layer (41) on the first cover surface (21a) and a second contact layer (42) on a second cover surface (3a) of the emission regions (3) facing away from the first semiconductor layer (21) in such a way that the first contact layer (41) and the second contact layer (42) are electrically separated from each other, and the first contact layer (41) and the second contact layer (42) run parallel to each other.

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