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    VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK
    21.
    发明申请
    VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK 有权

    公开(公告)号：US20070252617A1

    公开(公告)日：2007-11-01

    申请号：US11743625

    申请日：2007-05-02

    申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

    Multiplexing device including a hardwired multiplexer in a programmable logic device
    22.
    发明授权
    Multiplexing device including a hardwired multiplexer in a programmable logic device 有权
    多路复用器件包括可编程逻辑器件中的硬连线多路复用器

    公开(公告)号：US07253660B1

    公开(公告)日：2007-08-07

    申请号：US10305886

    申请日：2002-11-27

    申请人： Paul Leventis ,  Bruce Pedersen ,  Chris Lane ,  Srinivas Reddy ,  David Lewis

    发明人： Paul Leventis ,  Bruce Pedersen ,  Chris Lane ,  Srinivas Reddy ,  David Lewis

    IPC分类号： H01L25/00 ,  H03K19/177

    CPC分类号： H03K17/002

    摘要： A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.

    摘要翻译： 描述多路复用装置。 在一个实施例中，多路复用装置包括：硬连线多路复用器，包括多个输入端; 多个选择端子; 以及至少一个输出端子，其中多个输入端子耦合到多个块输入线或多个功能元件输入端子。 在一个实施例中，多个输入端子被硬连线到多个块输入线或多个功能元件输入端子。 在一个实施例中，多个选择端子耦合到第二多个功能元件输入端子或多个功能元件输出端子。 在一个实施例中，多个块输入线包括多个逻辑阵列块（LAB）线，多个功能元件输入端包括多个逻辑元件（LE）输入端，多个功能元件输出端包括 LE输出端子。 在另一实施例中，多路复用装置包括：硬连线多路复用器，包括多个数据信号输入端; 以及包括第一多个LE输出端子的第一多个LE，其中所述多个数据信号输入端子耦合到所述第一多个LE输出端子。

    Distributed memory in field-programmable gate array integrated circuit devices
    23.
    发明申请
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US20070146178A1

    公开(公告)日：2007-06-28

    申请号：US11320253

    申请日：2005-12-27

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Wong ,  Andy Lee ,  Philip Pan

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Wong ,  Andy Lee ,  Philip Pan

    IPC分类号： H03M7/00

    CPC分类号： G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    摘要翻译： 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

    Routing architecture for a programmable logic device
    24.
    发明授权
    Routing architecture for a programmable logic device 失效
    可编程逻辑器件的路由架构

    公开(公告)号：US06970014B1

    公开(公告)日：2005-11-29

    申请号：US10623709

    申请日：2003-07-21

    申请人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    发明人： David M. Lewis ,  Paul Leventis ,  Andy L. Lee ,  Brian D. Johnson ,  Richard Cliff ,  Srinivas T. Reddy ,  Christopher F. Lane ,  Cameron R. McClintock ,  Vaughn Betz ,  Chris Wysocki ,  Alexander R. Marquardt

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17736

    摘要： An embodiment of this invention pertains to a 3-sided routing architecture to interconnect function blocks, such as logic array blocks (“LABs”), within a programmable logic device (“PLD”). In the 3-sided routing architecture, inputs and outputs on a first side of a function block connect to a first channel, and inputs and outputs on a second side of the function block connect to a second channel where the second side is opposite the first side. Inputs and outputs on a third side of the function block connect to a third channel. A fourth channel associated with a fourth side of the function block, the fourth side opposite the third side, is coupled only to the first channel and the second channel. In one configuration, the inputs and outputs on each of the first side, the second side, and the third side have an equal number of inputs and outputs. In this configuration, each of the first channel, the second channel, and the third channel have the same width. In another configuration, the number of pins on one of the first side, the second side, or the third side differs from the number of pins on another one of those sides.

    摘要翻译： 本发明的实施例涉及在可编程逻辑器件（“PLD”）内互连诸如逻辑阵列块（“LAB”）的功能块的3边路由架构。 在三面路由架构中，功能块第一侧的输入和输出连接到第一通道，功能块第二侧上的输入和输出连接到第二通道，其中第二侧与第一通道相反 侧。 功能块第三侧的输入和输出连接到第三个通道。 与功能块的第四侧相关联的与第三侧相反的第四侧的第四通道仅耦合到第一通道和第二通道。 在一种配置中，第一侧，第二侧和第三侧中的每一个上的输入和输出具有相等数量的输入和输出。 在该配置中，第一通道，第二通道和第三通道中的每一个具有相同的宽度。 在另一种构造中，第一侧，第二侧或第三侧中的一个上的引脚数目与另一侧上的引脚数不同。

    Power-driven timing analysis and placement for programmable logic
    27.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US08099692B1

    公开(公告)日：2012-01-17

    申请号：US12953764

    申请日：2010-11-24

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。

    Simultaneous switching noise analysis using superposition techniques
    28.
    发明授权
    Simultaneous switching noise analysis using superposition techniques 有权
    使用叠加技术进行同步开关噪声分析

    公开(公告)号：US07983880B1

    公开(公告)日：2011-07-19

    申请号：US12034400

    申请日：2008-02-20

    申请人： Joshua David Fender ,  Paul Leventis

    发明人： Joshua David Fender ,  Paul Leventis

    IPC分类号： G06G7/00

    CPC分类号： G06F17/5036 ,  G06F17/504 ,  G06F2217/82

    摘要： Extended linear superposition methods, computer program products and systems to calculate Simultaneous Switching Noise (SSN) on victim Input/Output (I/O) pins of an electronic component caused by aggressor I/O pins is provided. A method includes calculating the quiet output voltage on a victim pin caused by the power supply only, and then calculating an aggressor noise response induced on the victim pin caused by a single aggressor pin and the power supply. To calculate SSN for a combination of aggressors, the SSNs for the different aggressors are linearly combined, and then the effects of the power supply are discounted by using the calculated quiet output voltage. Additionally, a linear victim substitution model is introduced to replace a full buffer model for a victim pin with a resistor with different resistance values depending on the induced voltage. Further, an alternate transmission line model is introduced to simplify SSN simulations of transmission lines.

    摘要翻译： 提供扩展线性叠加方法，计算机程序产品和系统，用于计算由侵入者I / O引脚引起的电子元件的受害者输入/输出（I / O）引脚上的同时开关噪声（SSN）。 一种方法包括计算仅由电源引起的受害者引脚上的安静输出电压，然后计算由单个攻击者引脚和电源引起的受害者引脚上的侵扰者噪声响应。 为了计算攻击者组合的SSN，不同攻击者的SSN线性组合，然后使用计算出的静音输出电压对电源的影响进行折扣。 另外，引入线性受害者替代模型，以根据感应电压用具有不同电阻值的电阻替代受害针的完整缓冲器模型。 此外，引入替代传输线模型以简化传输线的SSN仿真。