公开(公告)号：US20080299716A1

公开(公告)日：2008-12-04

申请号：US12176488

申请日：2008-07-21

申请人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

发明人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

IPC分类号： H01L21/337

CPC分类号： H01L29/808 ,  H01L29/1066

摘要： A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

摘要翻译： 结型场效应晶体管（JFET）可以制造具有阱区，阱区包括平均掺杂剂浓度基本上小于阱区的剩余部分的平均掺杂浓度的沟道区。 与阱区域的其余部分相比，沟道区域的较低平均掺杂浓度降低了JFET的夹断电压。

公开(公告)号：US07417270B2

公开(公告)日：2008-08-26

申请号：US10874479

申请日：2004-06-23

申请人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

发明人： Philip L. Hower ,  David A. Walch ,  John Lin ,  Steven L. Merchant

IPC分类号： H01L29/80

CPC分类号： H01L29/808 ,  H01L29/1066

摘要： A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

摘要翻译： 结型场效应晶体管（JFET）可以制造具有阱区，阱区包括平均掺杂剂浓度基本上小于阱区的剩余部分的平均掺杂浓度的沟道区。 与阱区域的其余部分相比，沟道区域的较低平均掺杂浓度降低了JFET的夹断电压。

公开(公告)号：US20080132066A1

公开(公告)日：2008-06-05

申请号：US12016443

申请日：2008-01-18

申请人： Tony T. Phan ,  William C. Loftin ,  John Lin ,  Philip L. Hower

发明人： Tony T. Phan ,  William C. Loftin ,  John Lin ,  Philip L. Hower

IPC分类号： H01L21/768

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/76838

摘要： The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

摘要翻译： 因此，本发明提供一种集成电路及其制造方法。 在一个实施例中，集成电路（100,1000）没有限制地包括位于晶片衬底（110,1010）之上的电介质层（120,1020），以及位于介电层上的半导体衬底（130,1030） 120,120），具有位于其中或其上的一个或多个晶体管器件（140,1040）的半导体衬底（130,1030）。 集成电路（100,1000）还可以包括完全延伸穿过半导体衬底（130,1030）和介电层（120,1020）的互连（170,1053），从而与晶片衬底（110,1010）电接触， 。

公开(公告)号：US07262109B2

公开(公告)日：2007-08-28

申请号：US11196087

申请日：2005-08-03

申请人： John Lin ,  Tony T. Phan ,  Philip L. Hower ,  William C. Loftin ,  Martin B. Mollat

发明人： John Lin ,  Tony T. Phan ,  Philip L. Hower ,  William C. Loftin ,  Martin B. Mollat

IPC分类号： H01L21/76

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).

公开(公告)号：US08878330B2

公开(公告)日：2014-11-04

申请号：US13567456

申请日：2012-08-06

申请人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

发明人： Hideaki Kawahara ,  Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin ,  Robert A. Neidorff

IPC分类号： H01L29/02 ,  H01L21/761 ,  H01L21/266

CPC分类号： H01L21/761 ,  H01L21/266

摘要： An integrated circuit containing a voltage divider having an upper resistor of unsilicided gate material over field oxide around a central opening and a drift layer under the upper resistor, an input terminal coupled to an input node of the upper resistor adjacent to the central opening in the field oxide and coupled to the drift layer through the central opening, a sense terminal coupled to a sense node on the upper resistor opposite from the input node, a lower resistor with a sense node coupled to the sense terminal and a reference node, and a reference terminal coupled to the reference node. A process of forming the integrated circuit containing the voltage divider.

摘要翻译： 一种集成电路，包括分压器，该分压器具有围绕中心开口的场氧化物上的非硅栅极材料的上电阻器，以及位于上电阻器下的漂移层的输入端子，所述输入端子与所述上电阻器的输入节点相邻， 场氧化物并通过中心开口耦合到漂移层，感测端子耦合到与输入节点相反的上电阻上的感测节点，具有耦合到感测端子的检测节点和参考节点的下电阻器，以及 参考终端耦合到参考节点。 形成包含分压器的集成电路的工艺。

公开(公告)号：US08476127B2

公开(公告)日：2013-07-02

申请号：US13284011

申请日：2011-10-28

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower

IPC分类号： H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/265 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

摘要： An integrated circuit containing a dual drift layer extended drain MOS transistor with an upper drift layer contacting a lower drift layer along at least 75 percent of a common length of the two drift layers. An average doping density in the lower drift layer is between 2 and 10 times an average doping density in the upper drift layer. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, using an epitaxial process. A process of forming an integrated circuit containing a dual drift layer extended drain MOS transistor with a lower drift extension under the body region and an isolation link which electrically isolates the body region, on a monolithic substrate.

摘要翻译： 一种包含双漂移层延伸漏极MOS晶体管的集成电路，其上部漂移层沿着两个漂移层的公共长度的至少75％与下部漂移层接触。 下漂移层中的平均掺杂密度在上漂移层中的平均掺杂密度的2至10倍。 一种形成集成电路的过程，该集成电路包含在体区内具有较低漂移延伸的双漂移层延伸漏极MOS晶体管，以及使用外延工艺电隔离体区的隔离链路。 一种形成集成电路的过程，该集成电路包含在主体区域具有较低漂移延伸的双漂移层延伸漏极MOS晶体管和在整体式衬底上电隔离体区的隔离链路。

公开(公告)号：US08461589B1

公开(公告)日：2013-06-11

申请号：US13489257

申请日：2012-06-05

申请人： Philip L. Hower ,  Barry Jon Male ,  Wilburn M. Miller

发明人： Philip L. Hower ,  Barry Jon Male ,  Wilburn M. Miller

IPC分类号： H01L23/36 ,  H01L23/58 ,  H01L23/34

CPC分类号： H01L23/345 ,  H01L22/14 ,  H01L23/3677 ,  H01L23/5228 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) includes a heated portion. The heated portion/IC includes a substrate having a topside semiconductor surface having circuitry configured to provide a circuit function. A pre-metal dielectric (PMD) layer is on the topside semiconductor surface. A metal interconnect stack is on the PMD. A trim portion includes one or more temperature sensitive circuit components which affect a temperature behavior of the IC. The heated portion extends over and beyond an area of the trim portion having an integrated heating structure including at least a first heater formed from a metal interconnect level that includes a first plurality of winding segments which have a varying pitch. A heat spreader formed from a second metal interconnect layer is between trim portion and the first heater. Thermal plugs are lateral to the temperature sensitive circuit components and thermally couple the heat spreader to the topside semiconductor surface.

摘要翻译： 集成电路（IC）包括加热部分。 加热部分/ IC包括具有顶侧半导体表面的基板，其具有被配置为提供电路功能的电路。 前金属电介质（PMD）层位于顶侧半导体表面上。 PMD上有一个金属互连堆叠。 修整部分包括影响IC的温度特性的一个或多个温度敏感电路部件。 加热部分延伸超过具有整体加热结构的修整部分的区域，该整体加热结构至少包括由金属互连级别形成的第一加热器，该第一加热器包括具有变化间距的第一多个绕组段。 由第二金属互连层形成的散热器在修剪部分和第一加热器之间。 热插头是温度敏感电路部件的侧面，并将散热器热耦合到顶侧半导体表面。

公开(公告)号：US08274131B2

公开(公告)日：2012-09-25

申请号：US12962159

申请日：2010-12-07

申请人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

发明人： Sameer P. Pendharkar ,  John Lin ,  Philip L. Hower ,  Steven L. Merchant

IPC分类号： H01L21/70

CPC分类号： H01L21/8249 ,  H01L21/76232 ,  H01L27/0623

摘要： A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.

摘要翻译： 一种半导体器件，包括在半导体衬底（115）上或半导体衬底（115）中的第一晶体管器件（130）和衬底上或衬底中的第二晶体管器件（132）。 该器件还包括位于第一晶体管器件和第二晶体管器件之间的绝缘沟槽（200）。 绝缘沟槽的至少一个上角（610）是衬底的横向平面（620）中的圆角。

公开(公告)号：US20110275210A1

公开(公告)日：2011-11-10

申请号：US13188162

申请日：2011-07-21

申请人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

发明人： Marie Denison ,  Sameer Pendharkar ,  Philip L. Hower ,  John Lin

IPC分类号： H01L21/28

CPC分类号： H01L29/7813 ,  H01L29/42368 ,  H01L29/66719 ,  H01L29/66734

摘要： An electronic device has a plurality of trenches formed in a semiconductor layer. A vertical drift region is located between and adjacent the trenches. An electrode is located within each trench, the electrode having a gate electrode section and a field plate section. A graded field plate dielectric having increased thickness at greater depth is located between the field plate section and the vertical drift region.

摘要翻译： 电子器件具有形成在半导体层中的多个沟槽。 垂直漂移区域位于沟槽之间和相邻的沟槽之间。 电极位于每个沟槽内，电极具有栅电极部分和场板部分。 在场板部分和垂直漂移区域之间设置具有较大深度的厚度增加的分级场板电介质。

公开(公告)号：US07989853B2

公开(公告)日：2011-08-02

申请号：US12537589

申请日：2009-08-07

申请人： Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

发明人： Pinghai Hao ,  Sameer Pendharkar ,  Philip L. Hower ,  Marie Denison

IPC分类号： H01L29/66 ,  H01L21/337

CPC分类号： H01L27/098 ,  H01L29/0649 ,  H01L29/1058 ,  H01L29/402 ,  H01L29/808

摘要： A dual channel JFET which can be integrated in an IC without adding process steps is disclosed. Pinch-off voltage is determined by lateral width of a first, vertical, channel near the source contact. Maximum drain voltage is determined by drain to gate separation and length of a second, horizontal, channel under the gate. Pinch-off voltage and maximum drain potential are dependent on lateral dimensions of the drain and gate wells and may be independently optimized. A method of fabricating the dual channel JFET is also disclosed.

摘要翻译： 公开了可以集成在IC中而不添加工艺步骤的双通道JFET。 夹断电压由源触点附近的第一垂直通道的横向宽度决定。 最大漏极电压由漏极到栅极间隔和栅极下方的第二个水平沟道的长度决定。 夹断电压和最大漏极电位取决于漏极和栅极阱的横向尺寸，并且可以独立优化。 还公开了制造双通道JFET的方法。