公开(公告)号：US20090042374A1

公开(公告)日：2009-02-12

申请号：US11718488

申请日：2005-10-28

申请人： Bartlomiej J. Pawlak ,  Philippe Meunier-Beillard

发明人： Bartlomiej J. Pawlak ,  Philippe Meunier-Beillard

IPC分类号： H01L21/265

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02694

摘要： A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation. A second SiGe buffer layer 14 is grown on the first SiGe buffer layer after annealing. This produces a relaxed SiGe layer 12, 14. Then, the strained layer of Si 16 is grown.

摘要翻译： 在Si衬底10上形成Si应变层16的方法包括在Si衬底10上形成第一SiGe缓冲层12.然后，第一SiGe缓冲层注入非晶化注入，以使第一SiGe缓冲层呈非晶态 离子注入。 退火后在第一SiGe缓冲层上生长第二SiGe缓冲层14。 这产生松弛的SiGe层12,14。然后，生长Si 16的应变层。

公开(公告)号：US08476675B2

公开(公告)日：2013-07-02

申请号：US12918524

申请日：2009-02-26

申请人： Philippe Meunier-Beillard ,  Johannes J. T. M. Donkers ,  Erwin Hijzen

发明人： Philippe Meunier-Beillard ,  Johannes J. T. M. Donkers ,  Erwin Hijzen

IPC分类号： H01L29/66

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66242 ,  H01L29/7378

摘要： A semiconductor device (10) comprising a bipolar transistor and a field 5 effect transistor within a semiconductor body (1) comprising a projecting mesa (5) within which are at least a portion of a collector region (22c and 22d) and a base region (33c) of the bipolar transistor. The bipolar transistor is provided with an insulating cavity (92b) provided in the collector region (22c and 22d). The insulating cavity (92b) may be provided by providing a layer (33a) in the collector region (22c), creating an access path, for example by selectively etching polysilicon towards monocrystalline, and removing a portion of the layer (33a) to provide the cavity using the access path. The layer (33a) provided in the collector region may be of SiGe:C. By blocking diffusion from the base region the insulating cavity (92b) provides a reduction in the base collector capacitance and can be described as defining the base contact.

摘要翻译： 一种半导体器件（10），包括在半导体本体（1）内的双极晶体管和场效应晶体管，包括突出的台面（5），其中集电极区域（22c和22d）的至少一部分和基极区域 （33c）。 双极晶体管设置有设置在集电区域（22c和22d）中的绝缘腔（92b）。 可以通过在集电极区域（22c）中设置层（33a）来提供绝缘腔（92b），从而产生存取路径，例如通过选择性地将多晶硅蚀刻成单晶，并去除层（33a）的一部分以提供 使用进入路径的空腔。 设置在集电区域中的层（33a）可以是SiGe：C。 通过阻挡从基极区域的扩散，绝缘腔（92b）提供基极集电极电容的减小，并且可以被描述为限定基极接触。

公开(公告)号：US08242500B2

公开(公告)日：2012-08-14

申请号：US13005435

申请日：2011-01-12

申请人： Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Tony Vanhoucke

发明人： Philippe Meunier-Beillard ,  Johannes Josephus Theodorus Marinus Donkers ,  Hans Mertens ,  Tony Vanhoucke

IPC分类号： H01L29/04

CPC分类号： H01L29/66242 ,  H01L29/1004 ,  H01L29/7378

摘要： Disclosed is a method of forming a heterojunction bipolar transistor (HBT), comprising depositing a first stack comprising an polysilicon layer (16) and a sacrificial layer (18) on a mono-crystalline silicon substrate surface (10); patterning the first stack to form a trench (22) extending to the substrate; depositing a silicon layer (24) over the resultant structure; depositing a silicon-germanium-carbon layer (26) over the resultant structure; selectively removing the silicon-germanium-carbon layer (26) from the sidewalls of the trench (22); depositing a boron-doped silicon-germanium-carbon layer (28) over the resultant structure; depositing a further silicon-germanium-carbon layer (30) over the resultant structure; depositing a boron-doped further silicon layer (32) over the resultant structure; forming dielectric spacers (34) on the sidewalls of the trench (22); filling the trench (22) with an emitter material (36); exposing polysilicon regions (16) outside the side walls of the trench by selectively removing the sacrificial layer (18) of the first stack; implanting boron impurities into the exposed polysilicon regions (16) to define base implants; and exposing the resultant structure to a thermal budget for annealing the boron impurities. A HBT formed by this method is also disclosed.

摘要翻译： 公开了一种形成异质结双极晶体管（HBT）的方法，包括在单晶硅衬底表面（10）上沉积包括多晶硅层（16）和牺牲层（18）的第一堆叠; 图案化第一堆叠以形成延伸到衬底的沟槽（22）; 在所得结构上沉积硅层（24）; 在所得结构上沉积硅 - 锗 - 碳层（26）; 从所述沟槽（22）的侧壁选择性地去除所述硅 - 锗 - 碳层（26）。 在所得结构上沉积硼掺杂的硅 - 锗 - 碳层（28）; 在所得结构上沉积另外的硅 - 锗 - 碳层（30）; 在所得结构上沉积硼掺杂的另外的硅层（32）; 在所述沟槽（22）的侧壁上形成介电间隔物（34）; 用发射体材料（36）填充沟槽（22）; 通过选择性地去除第一堆叠的牺牲层（18），在沟槽的侧壁外露出多晶硅区域（16）; 将硼杂质注入暴露的多晶硅区域（16）中以限定基底植入物; 并将所得结构暴露于用于退火硼杂质的热预算。 还公开了通过该方法形成的HBT。

公开(公告)号：US07867864B2

公开(公告)日：2011-01-11

申请号：US12160210

申请日：2007-01-04

申请人： Sebastien Nuttinck ,  Giberto Curatola ,  Erwin Hijzen ,  Philippe Meunier-Beillard

发明人： Sebastien Nuttinck ,  Giberto Curatola ,  Erwin Hijzen ,  Philippe Meunier-Beillard

IPC分类号： H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： The invention relates to a method of manufacturing a semiconductor device comprising a field effect transistor, in which method a semiconductor body of silicon with a substrate is provided at a surface thereof with a source region and a drain region of a first conductivity type which are situated above a buried isolation region and with a channel region, between the source and drain regions, of a second conductivity type, opposite to the first conductivity type, and with a gate region separated from the surface of the semiconductor body by a gate dielectric and situated above the channel region, wherein a mesa is formed in the semiconductor body in which the channel region is formed and wherein the source and drain regions are formed on both sides of the mesa in a semiconductor region that is formed using epitaxial growth, the source and drain regions thereby contacting the channel region.

摘要翻译： 本发明涉及一种制造半导体器件的方法，该半导体器件包括场效应晶体管，其中在其表面上提供具有衬底的硅半导体本体，其具有位于第一导电类型的源区和漏区 位于源极和漏极区之间的与第一导电类型相反的第二导电类型的沟道区，以及通过栅极电介质与半导体本体的表面分离的栅极区，位于 在沟道区域的上方，其中在形成沟道区的半导体本体中形成台面，并且其中源极和漏极区域形成在使用外延生长形成的半导体区域中的台面的两侧，源极和漏极区域 漏区，从而接触沟道区。

公开(公告)号：US07605060B2

公开(公告)日：2009-10-20

申请号：US10550853

申请日：2004-03-25

申请人： Philippe Meunier-Beillard ,  Mathieu Rosa Jozef Caymax

发明人： Philippe Meunier-Beillard ,  Mathieu Rosa Jozef Caymax

IPC分类号： H01L21/20

CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) comprising silicon is provided with an n-type doped semiconductor region (2) comprising silicon by means of an epitaxial deposition process, wherein the epitaxial deposition process of the n-type region is performed by positioning the semiconductor body (1) in an epitaxial reactor and introducing in the reactor a first gas stream comprising a carrier gas and further gas streams comprising a gaseous compound comprising silicon and a gaseous compound comprising an element from the fifth column of the periodic system of elements, while heating the semiconductor body (1) to a growth temperature (Tg) and using an inert gas as the carrier gas. According to the invention for the gaseous compound comprising silicon a mixture is chosen of a first gaseous silicon compound which is free of chlorine and a second gaseous silicon compound comprising chlorine. Such a method allows for a very high carrier concentration in the in-situ doped grown region (3). Nitrogen is the preferred carrier gas.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）具有包括硅的半导体本体（1），其通过外延沉积工艺设置有包含硅的n型掺杂半导体区域（2），其中外延沉积 通过将半导体主体（1）定位在外延反应器中并在反应器中引入包含载气的第一气流以及包含含有硅的气态化合物和气态化合物的气流，进行n型区的工艺，该气态化合物包含 元件，同时将半导体本体（1）加热至生长温度（Tg）并使用惰性气体作为载气。 根据本发明，对于包含硅的气态化合物，混合物选自不含氯的第一气态硅化合物和包含氯的第二气态硅化合物。 这种方法允许在原位掺杂的生长区域（3）中具有非常高的载流子浓度。 氮气是优选的载气。

公开(公告)号：US20090075447A1

公开(公告)日：2009-03-19

申请号：US10586810

申请日：2005-01-22

申请人： Philippe Meunier-Beillard ,  Petrus Magnee

发明人： Philippe Meunier-Beillard ,  Petrus Magnee

IPC分类号： H01L21/331

CPC分类号： H01L29/66287 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/0804

摘要： Fabrication of a mono-crystalline emitter using a combination of selective and differential growth modes. The steps include providing a trench (14) formed on a silicon substrate (16) having opposed silicon oxide side walls (12); selectively growing a highly doped mono-crystalline layer (18) on the silicon substrate in the trench; and non-selectively growing a silicon layer (20) over the trench in order to form an amorphous polysilicon layer over the silicon oxide sidewalls.

摘要翻译： 使用选择和差异生长模式的组合制造单晶发射体。 这些步骤包括提供形成在具有相对的氧化硅侧壁（12）的硅衬底（16）上的沟槽（14）; 在沟槽中的硅衬底上选择性地生长高掺杂单晶层（18）; 以及在沟槽上非选择性地生长硅层（20），以在氧化硅侧壁上形成非晶态多晶硅层。

公开(公告)号：US20080203434A1

公开(公告)日：2008-08-28

申请号：US12088719

申请日：2006-09-22

申请人： Philippe Meunier-Beillard ,  Raymond James Duffy ,  Prabhat Agarwal ,  Godfridus Adrianus Maria Hurkx

发明人： Philippe Meunier-Beillard ,  Raymond James Duffy ,  Prabhat Agarwal ,  Godfridus Adrianus Maria Hurkx

IPC分类号： H01L29/737 ,  H01L21/331

CPC分类号： H01L29/7378 ,  H01L29/0817 ,  H01L29/66242

摘要： The invention relates to a semiconductor device (10) with a substrate and a semiconductor body of silicon comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) which are respectively of the N-type conductivity, the P-type conductivity and the N-type conductivity by the provision of suitable doping atoms, wherein the base region (2) comprises a mixed crystal of silicon and germanium, the base region (2) is separated from the emitter region by an intermediate region (22) of silicon having a doping concentration which is lower than the doping concentration of the emitter region (1) and with a thickness smaller than the thickness of the emitter region (1) and the emitter region (1) comprises a sub-region comprising a mixed crystal of silicon and germanium which is positioned at the side of emitter region (1) remote from the intermediate region (22). According to the invention, the sub-region comprising the mixed crystal of silicon and germanium extend substantially through the whole emitter region (1) up to the interlace with the intermediate region (22) and the doping atoms of the emitter region (1) are arsenic atoms. Such a device has a very steep n-type doping profile (50) and a very steep p-type doping profile (20) at or within the intermediate region (22) and thus excellent high-frequency behavior with a high cut-off frequency (fr). Preferably the emitter region (1) is doped with an arsenic implantation (I) in its upper half, the final doping profile being formed after an RTA. The invention also comprises a method of manufacturing a device (10) according to the invention.

摘要翻译： 本发明涉及一种具有衬底和硅半导体本体的半导体器件（10），其包括具有发射极区（1），基极区（2）和集电极区（3）的双极晶体管，所述发射极区分别为N 通过提供合适的掺杂原子，P型导电性和N型导电性，其中基区（2）包括硅和锗的混合晶体，基极区（2）与发射极分离 通过具有低于发射极区域（1）的掺杂浓度的掺杂浓度并且具有小于发射极区域（1）和发射极区域（1）的厚度的厚度的硅的中间区域（22） 包括位于远离中间区域（22）的发射极区域（1）侧的硅和锗的混合晶体的子区域。 根据本发明，包括硅和锗的混合晶体的子区域基本上延伸穿过整个发射极区域（1）直到与中间区域（22）交错，并且发射极区域（1）的掺杂原子是 砷原子 这种器件在中间区域（22）处或中间区域（22）内具有非常陡峭的n型掺杂分布（50）和非常陡的p型掺杂分布（20），因此具有高截止频率的极好的高频特性 （fr）。 优选地，发射极区域（1）在其上半部分掺杂有砷注入（I），最后的掺杂分布在RTA之后形成。 本发明还包括一种制造根据本发明的装置（10）的方法。

公开(公告)号：US07394144B2

公开(公告)日：2008-07-01

申请号：US10594487

申请日：2005-03-29

申请人： Christelle Rochefort ,  Erwin A. Hijzen ,  Philippe Meunier-Beillard

发明人： Christelle Rochefort ,  Erwin A. Hijzen ,  Philippe Meunier-Beillard

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/336 ,  H01L21/764

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66712 ,  H01L29/7811

摘要： Consistent with an example embodiment, a reduced surface field effect type (RESURF) semiconductor device is manufactured having a drift region over a drain region. Trenches are formed through openings in mask. A trench insulating layer is deposited on the sidewalls and base of the trenches followed by an overetching step to remove the trench insulating layer from the base of the trenches as well as the top of the sidewalls of the trenches adjacent to the first major surface leaving exposed silicon at the top of the sidewalls of the trench and the base of the trenches. Silicon is selectively grown plugging the trenches with silicon plug (18) leaving void.

摘要翻译： 与示例性实施例一致，制造了在漏极区域上具有漂移区域的减小的表面场效应型（RESURF）半导体器件。 通过面罩中的开口形成沟槽。 沟槽绝缘层沉积在沟槽的侧壁和基底上，随后进行过蚀刻步骤以从沟槽的底部除去沟槽绝缘层以及与第一主表面相邻的沟槽的侧壁的顶部，留下暴露的 在沟槽的侧壁的顶部和沟槽的底部的硅。 硅被选择性地生长，用硅塞（18）堵塞沟槽，留下空隙。

公开(公告)号：US20060205185A1

公开(公告)日：2006-09-14

申请号：US10550853

申请日：2004-03-25

申请人： Philippe Meunier-Beillard ,  Mathieu Caymax

发明人： Philippe Meunier-Beillard ,  Mathieu Caymax

IPC分类号： H01L21/20 ,  C23C16/00 ,  H01L21/36

CPC分类号： C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262

摘要： The invention relates to a method of manufacturing a semiconductor device (10) with a semiconductor body (1) comprising silicon is provided with an n-type doped semiconductor region (2) comprising silicon by means of an epitaxial deposition process, wherein the epitaxial deposition process of the n-type region is performed by positioning the semiconductor body (1) in an epitaxial reactor and introducing in the reactor a first gas stream comprising a carrier gas and further gas streams comprising a gaseous compound comprising silicon and a gaseous compound comprising an element from the fifth column of the periodic system of elements, while heating the semiconductor body (1) to a growth temperature (Tg) and using an inert gas as the carrier gas. According to the invention for the gaseous compound comprising silicon a mixture is chosen of a first gaseous silicon compound which is free of chlorine and a second gaseous silicon compound comprising chlorine. Such a method allows for a very high carrier concentration in the in-situ doped grown region (3). Nitrogen is the preferred carrier gas.

摘要翻译： 本发明涉及一种制造半导体器件（10）的方法，该半导体器件（10）具有包括硅的半导体本体（1），其通过外延沉积工艺设置有包含硅的n型掺杂半导体区域（2），其中外延沉积 通过将半导体主体（1）定位在外延反应器中并在反应器中引入包含载气的第一气流以及包含含有硅的气态化合物和气态化合物的气流，进行n型区的工艺，该气态化合物包含 元件，同时将半导体本体（1）加热至生长温度（Tg）并使用惰性气体作为载气。 根据本发明，对于包含硅的气态化合物，混合物选自不含氯的第一气态硅化合物和包含氯的第二气态硅化合物。 这种方法允许在原位掺杂的生长区域（3）中具有非常高的载流子浓度。 氮气是优选的载气。

公开(公告)号：US08431966B2

公开(公告)日：2013-04-30

申请号：US12994113

申请日：2009-05-11

申请人： Philippe Meunier-Beillard ,  Erwin Hijzen ,  Johannes J. T. M. Donkers

发明人： Philippe Meunier-Beillard ,  Erwin Hijzen ,  Johannes J. T. M. Donkers

IPC分类号： H01L21/33 ,  H01L29/732

CPC分类号： H01L29/7378 ,  H01L29/66242

摘要： Methods for manufacturing a bipolar transistor semiconductor device are described, along with devices fabricated in accordance with the methods. The methods include the steps of forming a stack of layers over a semiconductor body comprising a window definition layer (18,38), a layer (20) of semiconductor material, a first insulating layer (22), and a second insulating layer (24) which is selectively etchable with respect to the first insulating layer. A trench (26) is then etched into the stack down to the window definition layer. The portion of the trench extending through the second insulating layer is widened to form a wider trench portion (28) therethrough. A window (36) is defined in the window definition layer which is aligned with the wider trench portion, and serves to define the base-collector or base-emitter junction in the finished device.

摘要翻译： 描述了制造双极晶体管半导体器件的方法以及根据该方法制造的器件。 所述方法包括以下步骤：在半导体主体上形成层叠层，其包括窗口界定层（18,38），半导体材料层（20），第一绝缘层（22）和第二绝缘层（24） ），其相对于第一绝缘层可选择性地蚀刻。 然后将沟槽（26）蚀刻到堆叠中，直到窗口定义层。 延伸穿过第二绝缘层的沟槽的部分被加宽以形成穿过其中的较宽的沟槽部分（28）。 在窗口定义层中限定窗口（36），其与较宽的沟槽部分对准，并且用于限定最终器件中的基极 - 集电极或基极 - 发射极结。