利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

86 条记录 (耗时 0.032 秒)

    Method and system for rapidly recovering data from a “sick” disk in a RAID disk group
    21.
    发明授权
    Method and system for rapidly recovering data from a “sick” disk in a RAID disk group 有权
    从RAID磁盘组中“病”磁盘快速恢复数据的方法和系统

    公开(公告)号：US07574623B1

    公开(公告)日：2009-08-11

    申请号：US11118896

    申请日：2005-04-29

    申请人： Atul Goel ,  Tomislav Grcanac ,  Stephen H. Strange ,  Rajesh Sundaram

    发明人： Atul Goel ,  Tomislav Grcanac ,  Stephen H. Strange ,  Rajesh Sundaram

    IPC分类号： G06F11/00

    CPC分类号： G06F11/008 ,  G06F11/1088

    摘要： A method and system for recovering data from a “sick” disk are described. One embodiment of the invention relates to a RAID-based storage system that predicts the failure of a disk (e.g., a “sick” disk) in a RAID disk group. Accordingly, the storage system allocates a target disk, selected from several spare disks, to replace the “sick” disk in the RAID disk group upon completion of a disk-to-disk copy operation. Once a target disk has been allocated, a disk-to-disk copy operation is initiated to copy data from the “sick” disk to the target disk, thereby preventing the need to reconstruct data on the “sick” disk if the “sick” disk actually fails. During the disk-to-disk copy operation, client-initiated disk access operations continue to be serviced. Upon completion of the disk-to-disk copy operation, the storage system reconfigures the RAID disk group by swapping the target disk with the “sick” disk.

    摘要翻译： 描述了从“病”盘恢复数据的方法和系统。 本发明的一个实施例涉及一种基于RAID的存储系统，其预测RAID磁盘组中的盘（例如，“病”磁盘）的故障。 因此，在完成磁盘到磁盘复制操作时，存储系统分配从多个备用磁盘中选择的目标磁盘来替换RAID磁盘组中的“病”磁盘。 一旦分配了目标磁盘，启动磁盘到磁盘复制操作，以将数据从“病态”磁盘复制到目标磁盘，从而防止在“病态”磁盘上重建数据，如果“病” 磁盘实际上失败。 在磁盘到磁盘复制操作期间，客户端启动的磁盘访问操作继续被服务。 在完成磁盘到磁盘复制操作后，存储系统通过用“病”磁盘交换目标磁盘来重新配置RAID磁盘组。

    Method and system for accurately calculating latency variation on an end-to-end path in a network
    24.
    发明授权
    Method and system for accurately calculating latency variation on an end-to-end path in a network 失效
    准确计算网络中端到端路径上的延迟变化的方法和系统

    公开(公告)号：US06975656B1

    公开(公告)日：2005-12-13

    申请号：US09537995

    申请日：2000-03-29

    申请人： Shreedhar Madhavapeddi ,  Yoram Bernet ,  Rajesh Sundaram ,  John Holmes

    发明人： Shreedhar Madhavapeddi ,  Yoram Bernet ,  Rajesh Sundaram ,  John Holmes

    IPC分类号： H04J3/06 ,  H04L12/28

    CPC分类号： H04L12/2854

    摘要： A high-resolution, per-packet measurement tool for analyzing a computer network that operates by sending a predetermined number of packets from a sender machine to a receiver machine with measurement information inserted into the packet. The system kernel at the sending machine stamps a sequence number and the sender's local time into the data section of each packet. When packets arrive at the receiver machine, they are similarly stamped by the receiving machine's kernel with the receiving machine's local time. The maintained packet information serves as the basis for latency analysis. For example, one set of latencies can be obtained with QoS mechanisms turned on, and another set with QoS mechanisms turned off, whereby the benefits of the QoS mechanisms can be accurately determined. To analyze the latencies, the present invention normalizes each time and each latency into relative latency information. Clock skew and timer jumps may be handled as part of the normalization.

    摘要翻译： 一种用于分析计算机网络的高分辨率，每分组测量工具，所述计算机网络通过将预定数量的分组从发送者机器发送到具有插入分组中的测量信息的接收机的操作。 发送机的系统内核将序列号和发送者的本地时间标记到每个数据包的数据部分。 当数据包到达接收机时，接收机的内核同样受到接收机的本地时间的打印。 维护的分组信息用作等待时间分析的基础。 例如，可以在启用了QoS机制的情况下获得一组延迟，并且关闭具有QoS机制的另一组，由此可以准确地确定QoS机制的优点。 为了分析延迟，本发明将每个时间和每个延迟归一化为相对等待时间信息。 时钟偏移和定时跳转可以作为归一化的一部分来处理。

    Measuring network jitter on application packet flows
    25.
    发明授权
    Measuring network jitter on application packet flows 失效
    测量应用程序包流中的网络抖动

    公开(公告)号：US06928473B1

    公开(公告)日：2005-08-09

    申请号：US09670157

    申请日：2000-09-26

    申请人： Rajesh Sundaram ,  Sanjay N. Kaniyar

    发明人： Rajesh Sundaram ,  Sanjay N. Kaniyar

    IPC分类号： G06F15/173 ,  H04L12/26

    CPC分类号： H04L43/50 ,  H04L43/087 ,  H04L43/106

    摘要： A method is described for measuring the jitter experienced by an application's network traffic. The measurement is based solely on packets sent or received by the application itself. The method does not alter the application's packets, in particular, it does not add a timestamp to the packets before they are sent. Instead, it creates a table that stores unique identifiers of the application's packets along with the time the packets are sent. On the receiving computer, a similar table is created that stores the unique packet identifiers along with the time the packets are received. Records of sent packets are associated with records of received packets so that the time a packet was sent can be compared to the time the same packet was received. The resulting data are processed to calculate network jitter and packet loss ratios.

    摘要翻译： 描述了一种测量应用程序网络流量所遇到的抖动的方法。 测量仅基于应用程序本身发送或接收的数据包。 该方法不会更改应用程序的数据包，特别是在发送数据包之前不会添加时间戳。 相反，它创建一个表，存储应用程序的数据包的唯一标识符以及数据包发送的时间。 在接收计算机上，创建一个类似的表，其中存储唯一的分组标识符以及接收到分组的时间。 已发送数据包的记录与接收到的数据包的记录相关联，因此可以将数据包发送的时间与接收到相同数据包的时间进行比较。 处理所得数据以计算网络抖动和丢包率。

    Method and apparatus for providing quality-of-service delivery facilities over a bus
    27.
    发明授权
    Method and apparatus for providing quality-of-service delivery facilities over a bus 有权
    通过公共汽车提供服务质量提供设施的方法和装置

    公开(公告)号：US06820150B1

    公开(公告)日：2004-11-16

    申请号：US09829880

    申请日：2001-04-11

    申请人： Joseph M. Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

    发明人： Joseph M. Joy ,  Georgios Chrysanthakopoulos ,  Rajesh Sundaram ,  Arvind Murching

    IPC分类号： G06F1300

    CPC分类号： H04L12/40058 ,  H04L12/40065 ,  H04L47/13 ,  H04L49/205

    摘要： The invention provides quality-of-service (QoS) delivery services over a computer bus having isochronous data transfer capabilities. A transmitting node on the bus transmits a message to an intended recipient indicating a requested bandwidth for a connection. If the intended recipient has sufficient resources, it allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits the data on the allocated channel. If the recipient cannot allocate a channel, it does not respond, and the transmitter thereafter detects a time-out condition and begins transmitting using a “best efforts” scheme (i.e., non-guaranteed time delivery). In a second variation, a receiving node detects that it is receiving large quantities of data from a transmitting node. In response, the receiving node allocates an isochronous data channel on the bus and notifies the transmitter of the allocated channel. Thereafter, the transmitter transmits using the allocated isochronous channel. In a third variation, multiple receiving nodes that need to receive streaming data from a single transmitting node share a common isochronous data channel. In any of these variations, each receiver can periodically transmit a “deadman” timer message on a broadcast channel to indicate that it is still receiving on a given channel. If a transmitter detects that the deadman timer has expired, it reverts to transmitting data using a “best-efforts” scheme. A transmitter can transmit both to receivers that can handle QoS services and those that cannot explicitly support QoS services.

    摘要翻译： 本发明通过具有同步数据传输能力的计算机总线提供服务质量（QoS）传递服务。 总线上的发送节点向指定的接收者发送指示所请求的连接带宽的消息。 如果预期的接收者有足够的资源，它将在总线上分配一个同步数据信道，并向发射机通知所分配的信道。 此后，发射机在分配的信道上发送数据。 如果接收者不能分配信道，则它不响应，并且发射机此后检测到超时条件，并且使用“尽力而为”的方案开始发送（即，非保证的时间传递）。 在第二变体中，接收节点检测到它正在从发送节点接收大量的数据。 作为响应，接收节点在总线上分配等时数据信道，并向发射机通知所分配的信道。 此后，发射机使用所分配的同步信道进行发射。 在第三变型中，需要从单个发射节点接收流数据的多个接收节点共享公共同步数据信道。 在这些变型中的任何一个中，每个接收机可以在广播信道上周期性地发送“死机”定时器消息，以指示它仍然在给定信道上接收。 如果发射机检测到死机定时器已经过期，则它将恢复为使用“尽力而为”方案发送数据。 发射机可以将两者传输到可以处理QoS服务的接收机和不能明确支持QoS服务的接收机。

    Pipeline architecture for scalable performance on memory
    28.
    发明授权
    Pipeline architecture for scalable performance on memory 有权
    管道架构，可在内存上实现可扩展的性能

    公开(公告)号：US08909849B2

    公开(公告)日：2014-12-09

    申请号：US12946612

    申请日：2010-11-15

    申请人： Rajesh Sundaram ,  Derchang Kau ,  David J. Zimmerman

    发明人： Rajesh Sundaram ,  Derchang Kau ,  David J. Zimmerman

    IPC分类号： G11C13/00 ,  G11C7/10

    CPC分类号： G11C13/0004 ,  G06F2213/0038 ,  G11C7/1039 ,  G11C13/0061 ,  G11C13/0069

    摘要： An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.

    摘要翻译： 提出了一种用于数据存储的设备。 在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。 该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。

    INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS
    30.
    发明申请
    INTERFACE FOR STORAGE DEVICE ACCESS OVER MEMORY BUS 有权
    用于存储器存储器的接口通过存储器总线访问

    公开(公告)号：US20140075107A1

    公开(公告)日：2014-03-13

    申请号：US14075765

    申请日：2013-11-08

    申请人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    发明人： Shekoufeh Qawami ,  Rajesh Sundaram ,  David J. Zimmerman ,  Robert W. Faber

    IPC分类号： G11C7/22

    CPC分类号： G06F13/28 ,  G06F1/12 ,  G06F12/0246 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/385 ,  G06F13/409 ,  G06F13/42 ,  G06F2212/7201 ,  G06F2212/7203 ,  G11C7/222 ,  H04L5/00 ,  H04L7/00 ,  Y02D10/14 ,  Y02D10/151

    摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.

    摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。