-
公开(公告)号：US20150269100A1
公开(公告)日：2015-09-24
申请号：US14731183
申请日：2015-06-04
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。
-
公开(公告)号：US08607089B2
公开(公告)日：2013-12-10
申请号：US13111839
申请日：2011-05-19
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
-
公开(公告)号：US20120297231A1
公开(公告)日：2012-11-22
申请号：US13111839
申请日：2011-05-19
IPC分类号： G06F1/12
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。
-
公开(公告)号：US20140075107A1
公开(公告)日：2014-03-13
申请号：US14075765
申请日：2013-11-08
IPC分类号： G11C7/22
CPC分类号： G06F13/28 , G06F1/12 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/385 , G06F13/409 , G06F13/42 , G06F2212/7201 , G06F2212/7203 , G11C7/222 , H04L5/00 , H04L7/00 , Y02D10/14 , Y02D10/151
摘要： A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends synchronous data access commands to the nonvolatile memory device, and reads the response from the device bus based on an expected timing of a reply from the nonvolatile memory device. The controller determines the expected timing based on when the command was sent, and characteristics of the nonvolatile memory device. The controller may not need all the electrical signal lines available on the memory bus, and could issue data access commands to different groups of nonvolatile memory devices over different groups of electrical signal lines. The memory bus may be available and configured for either use with a memory controller and volatile memory devices, or a storage controller and nonvolatile memory devices.
摘要翻译： 通过存储器总线访问非易失性存储器或存储器件。 存储器总线具有通常用于易失性存储器件的电接口。 耦合到总线的控制器向非易失性存储器件发送同步数据访问命令，并且基于来自非易失性存储器件的回复的期望定时从设备总线读取响应。 控制器基于何时发送命令和非易失性存储器件的特性来确定预期时序。 控制器可能不需要存储器总线上可用的所有电信号线，并且可以通过不同的电信号线组向不同组的非易失性存储器件发出数据访问命令。 存储器总线可以可用并且被配置用于与存储器控制器和易失性存储器设备或存储控制器和非易失性存储器设备一起使用。
-
公开(公告)号：US20130339589A1
公开(公告)日：2013-12-19
申请号：US13977084
申请日：2011-12-27
IPC分类号： G06F12/02
CPC分类号： G11C13/0038 , G06F1/3275 , G06F9/30101 , G06F12/0246 , G11C13/0004 , G11C13/0033 , G11C16/06 , Y02D10/14
摘要： Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
摘要翻译： 公开了用于非易失性存储器的自适应配置的示例。 示例包括配置为包括默认值和更新值以指示非易失性存储器的一个或多个配置的模式寄存器。 这些示例还可以包括可以指示存储器地址长度和/或操作功率状态的配置表中维护的可发现功能。
-
公开(公告)号：US09195589B2
公开(公告)日：2015-11-24
申请号：US13977084
申请日：2011-12-27
CPC分类号： G11C13/0038 , G06F1/3275 , G06F9/30101 , G06F12/0246 , G11C13/0004 , G11C13/0033 , G11C16/06 , Y02D10/14
摘要： Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.
摘要翻译： 公开了用于非易失性存储器的自适应配置的示例。 示例包括配置为包括默认值和更新值以指示非易失性存储器的一个或多个配置的模式寄存器。 这些示例还可以包括可以指示存储器地址长度和/或操作功率状态的配置表中维护的可发现功能。
-
公开(公告)号：US09274885B2
公开(公告)日：2016-03-01
申请号：US13997246
申请日：2011-12-30
申请人： Shekoufeh Qawami , Rajesh Sundaram
发明人： Shekoufeh Qawami , Rajesh Sundaram
CPC分类号： G06F11/1048 , G06F11/073 , G06F11/0763 , G06F11/1068 , G11C13/0004
摘要： Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。
-
公开(公告)号：US20140258804A1
公开(公告)日：2014-09-11
申请号：US13792597
申请日：2013-03-11
申请人： Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
发明人： Kiran Pangal , Prashant S. Damle , Rajesh Sundaram , Shekoufeh Qawami , Julie M. Walker , Doyle Rivers
IPC分类号： H03M13/05
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1044 , G06F11/1048 , G06F11/1068 , H03M13/05 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/27 , H03M13/6508
摘要： Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.
摘要翻译： 可以通过确定一组存储器阵列的逻辑阵列地址并且至少部分地基于该组内的至少两个存储器阵列的逻辑位置将逻辑阵列地址变换为至少两个唯一阵列地址来减少不可校正的存储器错误 的存储器阵列。 然后使用至少两个唯一的阵列地址分别访问至少两个存储器阵列。
-
公开(公告)号：US20140317474A1
公开(公告)日：2014-10-23
申请号：US13997246
申请日：2011-12-30
申请人： Shekoufeh Qawami , Rajesh Sundaram
发明人： Shekoufeh Qawami , Rajesh Sundaram
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F11/073 , G06F11/0763 , G06F11/1068 , G11C13/0004
摘要： Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.
摘要翻译： 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。
-
公开(公告)号：US08909849B2
公开(公告)日：2014-12-09
申请号：US12946612
申请日：2010-11-15
CPC分类号： G11C13/0004 , G06F2213/0038 , G11C7/1039 , G11C13/0061 , G11C13/0069
摘要： An apparatus for data storage is presented. In one embodiment, the apparatus includes a phase change memory device comprising phase change memory storage elements. The apparatus further includes control logic to control two or more set pipelines to serve memory requests in a staggered manner, such that set operations of the memory requests begin at different times.
摘要翻译： 提出了一种用于数据存储的设备。 在一个实施例中，该装置包括包括相变存储器存储元件的相变存储器件。 该装置还包括控制逻辑以控制两个或更多个集合管线以交错方式提供存储器请求，使得存储器请求的设置操作在不同时间开始。
-
-
-
-
-
-
-
-
-
搜索结果
86 条记录 (耗时 0.025 秒)