公开(公告)号：US09800230B1

公开(公告)日：2017-10-24

申请号：US15197589

申请日：2016-06-29

Applicant: QUALCOMM Incorporated

Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K5/00 ,  H03K3/012 ,  H03K17/22 ,  H03K3/037 ,  H03K5/19

CPC classification number: H03K3/012 ,  G06F1/24 ,  H03K3/0375 ,  H03K5/19 ,  H03K17/223

Abstract: A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.

公开(公告)号：US09735763B1

公开(公告)日：2017-08-15

申请号：US15083030

申请日：2016-03-28

Applicant: QUALCOMM Incorporated

Inventor： Wilson Chen ,  Chiew-Guan Tan ,  Sumit Rao

IPC: H03K5/08 ,  H03K19/003 ,  H03K5/24

CPC classification number: H03K5/08 ,  G06F13/4072 ,  H03K5/24 ,  H03K19/00315 ,  H03K19/018514

Abstract: An input receiver for stepping down a high power domain input signal for a high power domain powered by a high power supply voltage into an output signal for a low power domain includes a waveform splitter. The waveform splitter splits the high power domain input signal into a high voltage signal and a low voltage signal. A high voltage input receiver receives the high voltage signal to produce a received high voltage that is level shifted into a first input signal. A low voltage input receiver receives the low voltage signal to produce a second input signal. A logic circuit generates the output signal from the first input signal and the second input signal.

公开(公告)号：US09484911B2

公开(公告)日：2016-11-01

申请号：US14631347

申请日：2015-02-25

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K3/01 ,  H03K17/26 ,  H03K17/18

CPC classification number: H03K17/26 ,  H03K17/18 ,  H03K19/00315 ,  H03K19/00361

Abstract: A back-power prevention circuit is provided that protects a buffer transistor from back-power during a back-power condition by charging a signal lead coupled to a gate of the buffer transistor to a pad voltage and by charging a body of the buffer transistor to the pad voltage.

Abstract translation: 提供了一种后置功率防止电路，其通过将耦合到缓冲晶体管的栅极的信号引线充电到焊盘电压并且通过将缓冲晶体管的主体充电到基板来保护缓冲晶体管免受后功率状态下的反向功率 焊盘电压。

公开(公告)号：US20150333053A1

公开(公告)日：2015-11-19

申请号：US14805745

申请日：2015-07-22

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Brian Matthew Henderson ,  Shiqun Gu ,  Chiew-Guan Tan ,  Jung Pill Kim ,  Taehyun Kim

IPC: H01L27/02 ,  H01L23/48 ,  H01L29/66 ,  H01L21/304 ,  H01L29/861 ,  H01L21/762 ,  H01L29/06 ,  H01L27/08 ,  H01L21/768 ,  H01L29/872

CPC classification number: H01L29/66128 ,  H01L21/304 ,  H01L21/762 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/525 ,  H01L23/535 ,  H01L23/60 ,  H01L25/0657 ,  H01L27/0255 ,  H01L27/0296 ,  H01L27/0694 ,  H01L27/0814 ,  H01L29/0649 ,  H01L29/66143 ,  H01L29/8611 ,  H01L29/872 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/16145 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A method includes thinning a back-side of a substrate to expose a portion of a first via that is formed in the substrate. The method also includes forming a first diode at the back-side of the substrate. The first diode is coupled to the first via.

Abstract translation: 一种方法包括使衬底的背面变薄以暴露形成在衬底中的第一通孔的一部分。 该方法还包括在衬底的背面形成第一二极管。 第一二极管耦合到第一通孔。

公开(公告)号：US09184735B1

公开(公告)日：2015-11-10

申请号：US14254706

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: H03K5/08

CPC classification number: H03K5/08 ,  H03K5/24 ,  H03K19/00315

Abstract: An input receiver for stepping down a high-voltage domain input signal into a low-voltage-domain stepped-down signal includes a waveform chopper. The waveform chopper chops the high-voltage domain input signal into a first chopped signal and a second chopped signal. A high-voltage-domain receiver combines the first chopped signal and the second chopped signal into a high-voltage-domain combined signal. A step-down device converts the high-voltage-domain combined signal into a stepped-down low-voltage-domain signal.

Abstract translation: 用于将高电压域输入信号降压为低电压域降阶信号的输入接收器包括波形斩波器。 波形斩波器将高电压域输入信号切成第一斩波信号和第二斩波信号。 高电压域接收器将第一斩波信号和第二斩波信号组合成高电压域组合信号。 降压装置将高电压域组合信号转换成降压低电压域信号。

公开(公告)号：US20150042401A1

公开(公告)日：2015-02-12

申请号：US13962742

申请日：2013-08-08

Applicant: QUALCOMM INCORPORATED

Inventor： Stephen Knol ,  Michael Brunolli ,  Chiew-Guan Tan ,  Damen Redelings

IPC: G05F3/24

CPC classification number: H03K17/04123 ,  H03K2217/0054

Abstract: An input receiver includes a first pass transistor coupled between an input pad and an internal receiver node. The first pass transistor includes a controlled floating gate capacitively coupled to the input pad. A source follower transistor couples between the internal receiver node and a power supply. A gate for the source follower transistor couples to the input pad.

Abstract translation: 输入接收机包括耦合在输入焊盘和内部接收器节点之间的第一传输晶体管。 第一传输晶体管包括电容耦合到输入焊盘的受控浮动栅极。 源极跟随器晶体管耦合在内部接收器节点和电源之间。 源极跟随器晶体管的栅极耦合到输入焊盘。

公开(公告)号：US20140091860A1

公开(公告)日：2014-04-03

申请号：US13683053

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Wilson Jianbo Chen ,  Chiew-Guan Tan ,  Reza Jalilizeinali

IPC: G05F1/565

CPC classification number: G05F1/565

Abstract: An input/output (I/O) driver is disclosed that employs a compensation circuit to limit the voltages across devices of the driver from exceeding a defined threshold to allow lower voltage devices to implement the operation of the driver. In particular, the driver employs a pull-up circuit including first and second switching devices coupled between a first voltage rail and an output of the driver. The driver employs a pull-down circuit including third and fourth switching devices coupled between the output and a second voltage rail. The I/O driver employs a compensation circuit configured to apply a compensation voltage to the node between the first and second switching devices and to the node between the third and fourth switching devices at the appropriate times to maintain the respective voltages across the second and third switching devices at or below a defined threshold, such as a reliability limit, during the operation of the driver.

Abstract translation: 公开了一种输入/输出（I / O）驱动器，其采用补偿电路来限制驱动器的器件之间的电压超过限定的阈值，以允许较低电压的器件实现驱动器的操作。 特别地，驱动器采用包括耦合在第一电压轨和驱动器的输出之间的第一和第二开关器件的上拉电路。 驱动器采用包括耦合在输出端和第二电压轨道之间的第三和第四开关器件的下拉电路。 I / O驱动器采用补偿电路，其被配置为在适当的时间向第一和第二开关器件之间的节点和第三和第四开关器件之间的节点施加补偿电压，以保持跨越第二和第三开关器件的相应电压 在驾驶员的操作期间，切换设备处于或低于定义的阈值，例如可靠性限制。