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公开(公告)号：US20170090546A1
公开(公告)日：2017-03-30
申请号：US14863890
申请日：2015-09-24
Applicant: QUALCOMM Incorporated
Inventor： Michael Brunolli , Stephen Thilenius , Patrick Isakanian , Vaishnav Srinivas
IPC: G06F1/32 , G11C11/4074 , G11C7/10
CPC classification number: G06F1/3275 , G06F1/32 , G06F1/3209 , G06F1/3287 , G06F1/3296 , G06F13/16 , G06F13/4086 , G06F13/4243 , G11C7/1072 , G11C11/4074 , H04L25/0278 , Y02D10/14 , Y02D10/172 , Y02D50/20
Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.
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公开(公告)号：US20130214380A1
公开(公告)日：2013-08-22
申请号：US13859512
申请日：2013-04-09
Applicant: QUALCOMM Incorporated
Inventor： Behnam Malek-Khosravi , Michael Brunolli
CPC classification number: G06F17/505 , H01L27/04
Abstract: A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.
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公开(公告)号：US20150109030A1
公开(公告)日：2015-04-23
申请号：US14056913
申请日：2013-10-17
Applicant: QUALCOMM Incorporated
Inventor： Michael Brunolli , Mark Wayland
IPC: H03K3/01
CPC classification number: H03K3/01 , G11C7/1057 , H03K19/0005 , H03K19/00315 , H04L25/0278
Abstract: An output driver configured to drive an output node includes a pull-down section having a plurality of legs and a pull-up section having a plurality of pull-up legs. Each leg and pull-up leg includes a data path and a calibration path. The data paths in the pull-down section are configured to conduct to ground responsive to an assertion of a complement data output signal whereas the data paths in the pull-up section are configured to conduct to a power supply node responsive to a de-assertion of the complement data output signal.
Abstract translation: 配置为驱动输出节点的输出驱动器包括具有多个支脚的下拉部分和具有多个上拉支腿的上拉部分。 每个腿和上拉腿包括数据路径和校准路径。 下拉部分中的数据路径被配置为响应于补充数据输出信号的断言而导通到地，而上拉部分中的数据路径被配置为响应于断言而导向电源节点 的补码数据输出信号。
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公开(公告)号：US20150109023A1
公开(公告)日：2015-04-23
申请号：US14056904
申请日：2013-10-17
Applicant: QUALCOMM Incorporated
Inventor： Michael Brunolli , Mark Wayland
IPC: H03K19/00
CPC classification number: H03K19/0005 , H03K5/06 , H03K6/04 , H03K19/017545 , H03K19/018528 , H04L25/0278 , H04L25/05
Abstract: An output driver for driving a data output signal through an output pad includes a plurality of calibration paths to calibrate the impedance of the output pad. Depending upon the desired impedance, various ones of the calibration paths are selectively coupled to the output pad. Each selected calibration path adds a capacitive load to a data node, which affects the slew rate for the data output signal. To adjust the capacitive load on the data node in light of the calibration path selections, the output driver includes a plurality of selectable capacitors corresponding to the plurality of calibration paths. If a calibration path is not selected to couple to the output pad, the corresponding selectable capacitor capacitively loads the data node.
Abstract translation: 用于通过输出焊盘驱动数据输出信号的输出驱动器包括多个校准路径以校准输出焊盘的阻抗。 根据期望的阻抗，各种校准路径选择性地耦合到输出焊盘。 每个选定的校准路径将一个容性负载添加到数据节点，影响数据输出信号的转换速率。 为了根据校准路径选择来调整数据节点上的容性负载，输出驱动器包括对应于多个校准路径的多个可选择的电容器。 如果没有选择校准路径来耦合到输出焊盘，相应的可选择电容可以电容性地加载数据节点。
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5.发明申请公开(公告)号：US20140061642A1
公开(公告)日：2014-03-06
申请号：US13802759
申请日：2013-03-14
Applicant: QUALCOMM INCORPORATED
Inventor： Vaishnav Srinivas , Bernie Jord Yang , Michael Brunolli , David Ian West , Charles David Paynter
IPC: H01L23/00
CPC classification number: H01L24/17 , H01L21/563 , H01L22/32 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0556 , H01L2224/05569 , H01L2224/11462 , H01L2224/13028 , H01L2224/131 , H01L2224/13109 , H01L2224/13116 , H01L2224/13147 , H01L2224/14165 , H01L2224/16225 , H01L2224/16245 , H01L2224/27462 , H01L2224/29028 , H01L2224/29078 , H01L2224/29147 , H01L2224/3012 , H01L2224/3213 , H01L2224/73204 , H01L2224/81193 , H01L2224/81815 , H01L2224/831 , H01L2924/00014 , H01L2924/01322 , H01L2924/07802 , H01L2924/381 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.
Abstract translation: 这里描述了使用外部互连在芯片的内部部分中布线管芯信号的方法的各个方面。 该方法提供了耦合到管芯内部的电路的触点，其中触点暴露于管芯的外部部分。 外部互连被配置为耦合这些触点，使得来自芯片内部部分的电路的信号可以被外部引导到管芯。 在所公开的方法的各个方面，外部互连由模具的包装保护。
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Patent Agency Ranking
公开(公告)号：US09871012B2
公开(公告)日：2018-01-16
申请号：US13802759
申请日：2013-03-14
Applicant: QUALCOMM Incorporated
Inventor： Vaishnav Srinivas , Bernie Jord Yang , Michael Brunolli , David Ian West , Charles David Paynter
CPC classification number: H01L24/17 , H01L21/563 , H01L22/32 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/27 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/81 , H01L24/83 , H01L2224/02377 , H01L2224/0401 , H01L2224/05558 , H01L2224/0556 , H01L2224/05569 , H01L2224/11462 , H01L2224/13028 , H01L2224/131 , H01L2224/13109 , H01L2224/13116 , H01L2224/13147 , H01L2224/14165 , H01L2224/16225 , H01L2224/16245 , H01L2224/27462 , H01L2224/29028 , H01L2224/29078 , H01L2224/29147 , H01L2224/3012 , H01L2224/3213 , H01L2224/73204 , H01L2224/81193 , H01L2224/81815 , H01L2224/831 , H01L2924/00014 , H01L2924/01322 , H01L2924/07802 , H01L2924/381 , H01L2924/0105 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
Abstract: Various aspects of an approach for routing die signals in an interior portion of a die using external interconnects are described herein. The approach provides for contacts coupled to circuits in the interior portion of the die, where the contacts are exposed to an exterior portion of the die. The external interconnects are configured to couple these contacts so that signals from the circuits in the interior portion of the die may be routed externally to the die. In various aspects of the disclosed approach, the external interconnects are protected by a packaging for the die.
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公开(公告)号：US20170017587A1
公开(公告)日：2017-01-19
申请号：US15204755
申请日：2016-07-07
Applicant: QUALCOMM Incorporated
Inventor： David West , Vaishnav Srinivas , Michael Brunolli , Jungwon Suh
CPC classification number: G06F13/1689 , G06F13/4068 , G06F2213/0038 , G11C7/222 , H03L7/0807 , Y02D10/14 , Y02D10/151
Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command dock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.
Abstract translation: 公开了在自适应通信接口中使用的方法，装置和系统。 提供了一种自适应通信接口，其中在低功率操作模式中抑制了以高速操作模式提供的高速时钟。 在低功耗操作模式下，低速指令基座用于存储器件与片上系统，应用处理器或其他器件之间的数据传输。 用于操作自适应通信接口的方法可以包括使用第一时钟信号来通过命令总线控制对存储器设备的命令的传输。 在第一操作模式中，第一时钟信号控制通过自适应通信接口的数据传输。 在第二种操作模式中，第二时钟信号通过自适应通信接口控制数据传输。 第二时钟信号的频率可以大于第一时钟信号的频率。
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公开(公告)号：US10169262B2
公开(公告)日：2019-01-01
申请号：US15204755
申请日：2016-07-07
Applicant: QUALCOMM Incorporated
Inventor： David West , Vaishnav Srinivas , Michael Brunolli , Jungwon Suh
Abstract: Methods, apparatus, and system for use in adaptive communication interfaces are disclosed. An adaptive communication interface is provided, in which a high-speed clock provided in a high-speed mode of operation is suppressed in a low-power mode of operation. In the low-power mode of operation, a low-speed command clock is used for data transfers between a memory device and a system-on-chip, applications processor or other device. A method for operating the adaptive communication interface may include using a first clock signal to control transmissions of commands to a memory device over a command bus. In a first mode of operation, the first clock signal controls data transmissions over the adaptive communication interface. In a second mode of operation, the second clock signal controls data transmissions over the adaptive communication interface. The frequency of the second clock signal may be greater than the frequency of the first clock signal.
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公开(公告)号：US09910482B2
公开(公告)日：2018-03-06
申请号：US14863890
申请日：2015-09-24
Applicant: QUALCOMM Incorporated
Inventor： Michael Brunolli , Stephen Thilenius , Patrick Isakanian , Vaishnav Srinivas
CPC classification number: G06F1/3275 , G06F1/32 , G06F1/3209 , G06F1/3287 , G06F1/3296 , G06F13/16 , G06F13/4086 , G06F13/4243 , G11C7/1072 , G11C11/4074 , H04L25/0278 , Y02D10/14 , Y02D10/172 , Y02D50/20
Abstract: A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.
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公开(公告)号：US09083176B2
公开(公告)日：2015-07-14
申请号：US13740102
申请日：2013-01-11
Applicant: QUALCOMM Incorporated
Inventor： Eugene Robert Worley , Sreeker Dundigal , Evan Siansuri , Reza Jalilizeinali , Michael Brunolli
CPC classification number: H02H9/046 , G06F1/305 , H01L23/62 , H01L2924/0002 , H02H9/043 , H01L2924/00
Abstract: In a particular embodiment, a circuit includes a power supply, a ground, and a clamping transistor circuit coupled to the power supply and to the ground. The circuit further includes a disable clamp circuit. The disable clamp circuit is coupled to the power supply and is responsive to a second power supply input to selectively disable the clamping transistor circuit by modifying a charging current applied to a capacitor of the clamping transistor circuit. In a particular embodiment, modifying the charging current includes enabling a second charging path. Enabling the second charging path enables charging the capacitor at a higher charging rate than a charging rate associated with charging the capacitor via a first charging path.
Abstract translation: 在特定实施例中，电路包括耦合到电源和接地的电源，接地和钳位晶体管电路。 电路还包括禁止钳位电路。 禁止钳位电路耦合到电源，并且响应于第二电源输入，以通过修改施加到钳位晶体管电路的电容器的充电电流来选择性地禁止钳位晶体管电路。 在特定实施例中，修改充电电流包括实现第二充电路径。 启用第二充电路径使得能够以比通过第一充电路径对电容器充电相关的充电速率更高的充电速率对电容器进行充电。
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