公开(公告)号：US20150333005A1

公开(公告)日：2015-11-19

申请号：US14795914

申请日：2015-07-10

Applicant: QUALCOMM Incorporated

Inventor： Kambiz Samadi ,  Shreepad Amar Panth ,  Pratyush Kamal ,  Yang Du

IPC: H01L23/522 ,  G06F17/50 ,  H01L27/06

CPC classification number: H01L23/5226 ,  G06F17/5072 ,  G06F17/5081 ,  H01L25/0657 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.

Abstract translation: 公开了使用聚类来增加可用空白位置的单片三维（3D）集成电路（IC）（3DIC）中的单片间通道（MIV））。 在一个实施例中，提供了使用聚类将MIV放置在单片3DIC中的方法。 该方法包括确定在初始3DIC布局图中是否有多个MIV的多个初始MIV布置内是否包括任何MIV布局群集。 该方法还包括在初始3DIC布局图中的每个MIV放置簇内的多个MIV中的每个MIV在每个MIV放置簇的最终MIV放置处对齐以提供聚集的3DIC布局图。

公开(公告)号：US09053960B2

公开(公告)日：2015-06-09

申请号：US13784811

申请日：2013-03-04

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Mukul Gupta ,  Foua Vang

IPC: H01L27/07 ,  H01L27/08 ,  H01L29/66 ,  H01L27/01 ,  H01L29/94

CPC classification number: H01L27/0811 ,  H01L27/016 ,  H01L29/66181 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor having first, second and third nodes. The first and second nodes of the first transistor are connected together and the first and second nodes of the second transistor are connected together. The third node of the first transistor is connected to the third node of the second transistor. Each of the third nodes is constructed so that each node comprises a width and a length that is at least ten percent of the width.

Abstract translation: 集成电路包括具有第一，第二和第三节点的电容器。 第一晶体管的第一和第二节点连接在一起，第二晶体管的第一和第二节点连接在一起。 第一晶体管的第三节点连接到第二晶体管的第三节点。 每个第三节点被构造成使得每个节点包括宽度和至少占宽度百分之十的长度。

公开(公告)号：US20150112646A1

公开(公告)日：2015-04-23

申请号：US14132377

申请日：2013-12-18

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/06

Abstract: Methods of designing three dimensional integrated circuits (3DIC) and related systems and components are disclosed. An exemplary embodiment provides an improved cell library for use with existing place and route software in such a manner that the modified software allows building 3DICs. The improved cell library includes 3D cells that have the footprint of the cell projected onto a two dimensional (2D) image. The projected view may then be discounted to the portion of the cell that is within an upper tier so that the cell appears to the place and route software to be a 2D cell. The discounted 2D image is then used by the place and route software. Such cells allow a circuit designer to leverage the existing 2D place and route tools as well as static timing analysis tools.

Abstract translation: 公开了设计三维集成电路（3DIC）及相关系统和组件的方法。 示例性实施例提供了一种改进的小区库，其用于与现有的位置和路由软件一起使用，使得修改的软件允许构建3DIC。 改进的细胞库包括具有投影到二维（2D）图像上的细胞的足迹的3D细胞。 然后可以将投影视图折扣到上层内的单元的部分，使得单元格出现在该位置并将软件路由为2D单元。 打折的2D图像然后由地方和路线软件使用。 这样的单元允许电路设计者利用现有的2D位置和路径工具以及静态时序分析工具。

公开(公告)号：US20150109843A1

公开(公告)日：2015-04-23

申请号：US14152248

申请日：2014-01-10

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du ,  Kambiz Samadi

IPC: G11C5/02 ,  H01L23/00 ,  H04L12/933

CPC classification number: G11C5/02 ,  G06F1/3225 ,  G06F1/3275 ,  G11C5/025 ,  G11C5/063 ,  H01L24/89 ,  H01L27/0688 ,  H01L2924/1434 ,  H04L49/101 ,  H04L49/109 ,  Y02D10/13 ,  Y02D10/14

Abstract: Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components are disclosed. A 3D memory crossbar architecture with tight-pitched vertical monolithic intertier vias (MIVs) for inter-block routing and multiplexers at each tier for block access is used to shorten overall conductor length and reduce resistive-capacitive (RC) delay. Elimination of such long crossbars reduces the RC delay of the crossbar and generally improves performance and speed. Further, elimination of the long horizontal crossbars makes conductor routing easier. The MIVs, with their small run-length, can work without the need for repeaters (unlike the long crossbars), and control logic may be used to configure the memory banks based on use.

Abstract translation: 公开了具有垂直存储器组件的单片三维（3D）集成电路（IC）（3DIC）。 使用具有用于块间路由选择的紧密垂直单片中间层通道（MIV）的三维存储器交叉结构架构，用于块访问的每层级多路复用器，以缩短整体导体长度并降低电阻 - 电容（RC）延迟。 消除这种长的十字准线会降低交叉开关的RC延迟，并通常提高性能和速度。 此外，消除长的横向横梁使得导线布线更容易。 MIVs具有较小的长度，可以在不需要中继器的情况下工作（与长十字准线不同），并且可以使用控制逻辑来基于使用配置存储体。

公开(公告)号：US09013235B2

公开(公告)日：2015-04-21

申请号：US14012445

申请日：2013-08-28

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: H01L25/00 ,  H03K3/037 ,  G06F17/50

CPC classification number: H03K3/0372 ,  G06F17/5068 ,  H01L27/0688 ,  H03K3/35625

Abstract: Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods are disclosed. The present disclosure provides a 3D integrated circuit (IC) (3DIC) that has a flop spread across at least two tiers of the 3DIC. The flop is split across tiers with transistor partitioning in such a way that keeps all the clock related devices at the same tier, thus potentially giving better setup, hold and clock-to-q margin. In particular, a first tier of the 3DIC has the master latch, slave latch, and clock circuit. A second tier has the input circuit and the output circuit.

Abstract translation: 公开了具有最小时钟偏移和相关系统和方法的单片三维（3D）触发器。 本公开提供了具有翻转的3D集成电路（3DIC）（3DIC），其跨越3DIC的至少两层。 触发器分为跨级别，晶体管分区，使得所有与时钟相关的器件保持在同一层级，从而可能提供更好的设置，保持和时钟到余裕。 特别地，3DIC的第一层具有主锁存器，从锁存器和时钟电路。 第二层有输入电路和输出电路。

公开(公告)号：US20150019802A1

公开(公告)日：2015-01-15

申请号：US14012478

申请日：2013-08-28

Applicant: QUALCOMM Incorporated

Inventor： Pratyush Kamal ,  Yang Du

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G11C5/025 ,  G11C8/12 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/11

Abstract: A monolithic three dimensional (3D) memory cell array architecture with bitcell and logic partitioning is disclosed. A 3D integrated circuit (IC) (3DIC) is proposed which folds or otherwise stacks elements of the memory cells into different tiers within the 3DIC. Each tier of the 3DIC has memory cells as well as access logic including global block control logic therein. By positioning the access logic and global block control logic in each tier with the memory cells, the length of the bit and word lines for each memory call are shortened, allowing for reduced supply voltages as well as generally reducing the overall footprint of the memory device.

Abstract translation: 公开了一种具有位单元和逻辑分区的单片三维（3D）存储单元阵列架构。 提出了3D集成电路（IC）（3DIC），其将存储器单元的元素折叠或以其它方式叠加到3DIC内的不同层中。 3DIC的每一层具有存储单元以及包括其中的全局块控制逻辑的访问逻辑。 通过将访问逻辑和全局块控制逻辑定位在具有存储器单元的每个层中，每个存储器调用的位和字线的长度被缩短，允许减小的电源电压以及通常减小存储器件的总体占用 。

公开(公告)号：US20140124868A1

公开(公告)日：2014-05-08

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM INCORPORATED

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域之上，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。