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    MRAM SELF-REPAIR WITH BIST LOGIC
    21.
    发明申请
    MRAM SELF-REPAIR WITH BIST LOGIC 有权
    MRAM自我修复与BIST LOGIC

    公开(公告)号：US20140211551A1

    公开(公告)日：2014-07-31

    申请号：US13756136

    申请日：2013-01-31

    Applicant: QUALCOMM INCORPORATED

    Inventor： Jung Pill Kim ,  Taehyun Kim ,  Xia Li ,  Seung H. Kang

    IPC: G11C29/44 ,  G11C11/16

    CPC classification number: G11C29/4401 ,  G11C11/15 ,  G11C11/155 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1675 ,  G11C29/12 ,  G11C2029/1208 ,  G11C2029/4402

    Abstract: Memory self-repair circuitry includes a memory cell array on a chip, and built-in self test (BIST) circuitry on the chip coupled to the memory cell array. The BIST circuitry is configured to perform a magnetic random access memory (MRAM) write operation to write addresses of failed memory cells in the memory cell array to a failed address sector also in the memory cell array. The memory self-repair circuitry also includes first select circuitry coupled between the BIST circuitry and the memory cell array. The first select circuitry is configured to selectively couple an output of the BIST circuitry and an input to the memory cell array.

    Abstract translation: 存储器自修复电路包括芯片上的存储单元阵列，以及耦合到存储单元阵列的芯片上的内置自测试（BIST）电路。 BIST电路被配置为执行磁随机存取存储器（MRAM）写入操作，以将存储器单元阵列中的故障存储器单元的地址写入存储器单元阵列中的故障地址扇区。 存储器自修复电路还包括耦合在BIST电路和存储单元阵列之间的第一选择电路。 第一选择电路被配置为选择性地将BIST电路的输出和输入耦合到存储单元阵列。

    HIERARCHICAL MEMORY MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) ARCHITECTURE
    22.
    发明申请
    HIERARCHICAL MEMORY MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) ARCHITECTURE 有权
    分层存储器磁阻随机存取存储器（MRAM）架构

    公开(公告)号：US20130279244A1

    公开(公告)日：2013-10-24

    申请号：US13842122

    申请日：2013-03-15

    Applicant: QUALCOMM INCORPORATED

    Inventor： Seung H. Kang ,  Xiaochun Zhu

    IPC: G11C11/16 ,  H01L43/02

    CPC classification number: G11C11/161 ,  G06F12/0811 ,  G06F12/0893 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/222 ,  G11C11/1675 ,  G11C11/1693 ,  H01L43/02

    Abstract: A hierarchical memory magnetoresistive random-access memory architecture is disclosed. In a particular embodiment, an apparatus includes a first magnetoresistive random-access memory (MRAM) device corresponding to a first level in a hierarchical memory system. The apparatus includes a second MRAM device corresponding to a second level in the hierarchical memory system. The first MRAM device has a first access latency and includes a first magnetic tunnel junction (MTJ) device having a first physical configuration. The second MRAM device has a second access latency and includes a second WI device having a second physical configuration. The first access latency is less than the second access latency.

    Abstract translation: 公开了分层存储器磁阻随机存取存储器架构。 在特定实施例中，装置包括对应于分层存储器系统中的第一级的第一磁阻随机存取存储器（MRAM）装置。 该装置包括对应于分级存储器系统中的第二级的第二MRAM设备。 第一MRAM设备具有第一访问延迟并且包括具有第一物理配置的第一磁隧道结（MTJ）设备。 第二MRAM设备具有第二接入延迟并且包括具有第二物理配置的第二WI设备。 第一个访问延迟小于第二个访问延迟。

    MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION
    23.
    发明申请
    MAGNETIC TUNNEL JUNCTION DEVICE AND FABRICATION 有权
    磁性隧道连接装置和制造

    公开(公告)号：US20130235656A1

    公开(公告)日：2013-09-12

    申请号：US13872338

    申请日：2013-04-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

    IPC: H01L43/02 ,  G11C11/15

    CPC classification number: H01L43/02 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

    Abstract: An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.

    Abstract translation: 一种装置包括包括围绕金属垫的底盖层的结构。 该装置还包括磁隧道结（MTJ）装置，其包括耦合到该结构的底部电极。 MTJ装置包括磁性隧道结层，顶部电极和逻辑帽层。 MTJ装置相对于金属垫偏移。

    LATCHING CIRCUIT
    24.
    发明申请
    LATCHING CIRCUIT 有权
    锁定电路

    公开(公告)号：US20130182500A1

    公开(公告)日：2013-07-18

    申请号：US13785338

    申请日：2013-03-05

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/009

    Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.

    Abstract translation: 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过基于电阻的存储元件的电流。

    PHYSICALLY UNCLONABLE FUNCTION BASED ON THE RANDOM LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY
    29.
    发明申请
    PHYSICALLY UNCLONABLE FUNCTION BASED ON THE RANDOM LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY 有权
    基于随机随机存取存储器的随机逻辑状态的物理不可靠函数

    公开(公告)号：US20150071431A1

    公开(公告)日：2015-03-12

    申请号：US14072634

    申请日：2013-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

    IPC: G11C11/16 ,  H04L9/30

    CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

    Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.

    Abstract translation: 一个特征涉及实现物理不可克隆功能（PUF）的方法。 该方法包括将磁阻随机存取存储器（MRAM）阵列阵列暴露于正交外部磁场。 MRAM单元各自被配置为表示第一逻辑状态和第二逻辑状态之一，并且正交外部磁场定向为与MRAM单元的自由层的容易轴正交的方向，以将MRAM单元置于 不是第一逻辑状态或第二逻辑状态的中性逻辑状态。 该方法还包括去除正交的外部磁场，将阵列的每个MRAM单元随机地置于第一逻辑状态或第二逻辑状态中。

    PHYSICALLY UNCLONABLE FUNCTION BASED ON THE INITIAL LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY
    30.
    发明申请
    PHYSICALLY UNCLONABLE FUNCTION BASED ON THE INITIAL LOGICAL STATE OF MAGNETORESISTIVE RANDOM-ACCESS MEMORY 有权
    基于磁性随机存取存储器的初始逻辑状态的物理不可靠函数

    公开(公告)号：US20150071430A1

    公开(公告)日：2015-03-12

    申请号：US14072599

    申请日：2013-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

    IPC: G11C11/16 ,  H04L9/30

    CPC classification number: G11C11/1673 ,  G09C1/00 ,  G11C11/161 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

    Abstract: One feature pertains to a method for implementing a physically unclonable function (PUF). The method includes providing an array of magnetoresistive random access memory (MRAM) cells, where the MRAM cells are each configured to represent one of a first logical state and a second logical state. The array of MRAM cells are un-annealed and free from exposure to an external magnetic field oriented in a direction configured to initialize the MRAM cells to a single logical state of the first and second logical states. Consequently, each MRAM cell has a random initial logical state of the first and second logical states. The method further includes sending a challenge to the MRAM cell array that reads logical states of select MRAM cells of the array, and obtaining a response to the challenge from the MRAM cell array that includes the logical states of the selected MRAM cells of the array.

    Abstract translation: 一个特征涉及用于实现物理不可克隆功能（PUF）的方法。 该方法包括提供磁阻随机存取存储器（MRAM）单元阵列，其中MRAM单元被配置为表示第一逻辑状态和第二逻辑状态之一。 MRAM单元的阵列是未退火的，并且没有暴露于被配置为将MRAM单元初始化的方向定向到第一和第二逻辑状态的单个逻辑状态的外部磁场。 因此，每个MRAM单元具有第一和第二逻辑状态的随机初始逻辑状态。 该方法还包括向MRAM单元阵列发送挑战，该MRAM单元阵列读取阵列的选择MRAM单元的逻辑状态，以及从包括阵列的所选MRAM单元的逻辑状态的MRAM单元阵列获得对挑战的响应。

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