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    INVALID WRITE PREVENTION FOR STT-MRAM ARRAY
    3.
    发明申请
    INVALID WRITE PREVENTION FOR STT-MRAM ARRAY 审中-公开
    STT-MRAM阵列的无效写防

    公开(公告)号：US20130215675A1

    公开(公告)日：2013-08-22

    申请号：US13853146

    申请日：2013-03-29

    Applicant: Qualcomm Incorporated

    Inventor： Kyungho Ryu ,  Jisu Kim ,  Seong-Ook Jung ,  Seung H. Kang

    IPC: G11C11/16 ,  H01L43/12

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  H01L43/12 ,  Y10T29/4902

    Abstract: In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.

    Abstract translation: 在自旋转移力矩磁阻随机存取存储器（STT-MRAM）中，位单元阵列可以具有基本上平行于字线的源极线。 源极线可以基本上垂直于位线。 源极线控制单元包括公共源极线驱动器和被配置为选择各个源极线的源极线选择器。 源极线驱动器和源极线选择器可以以多路复用关系耦合。 位线控制单元包括公共位线驱动器和复用关系的位线选择器。 位线控制单元包括耦合在公共源线驱动器和位线选择线和位线之间的正沟道金属氧化物半导体（PMOS）元件。

    Constant sensing current for reading resistive memory
    5.
    发明授权
    Constant sensing current for reading resistive memory 有权
    用于读取电阻性存储器的恒定感应电流

    公开(公告)号：US09502088B2

    公开(公告)日：2016-11-22

    申请号：US14499155

    申请日：2014-09-27

    Applicant: QUALCOMM Incorporated

    Inventor： Seong-Ook Jung ,  Sara Choi ,  Jisu Kim ,  Taehui Na ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/16 ,  G11C7/14 ,  G11C7/06 ,  G11C7/08 ,  G11C13/00

    CPC classification number: G11C11/1673 ,  G11C7/062 ,  G11C7/08 ,  G11C7/14 ,  G11C13/004 ,  G11C2013/0045 ,  G11C2013/0054

    Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.

    Abstract translation: 系统和方法涉及提供用于读取电阻式存储器元件的恒定感测电流。 负载电压发生器基于配置为提供与过程电压 - 温度变化不变的恒定电流的电流镜提供负载电压。 基于所产生的负载电压，通过将从恒定电流反射的感测电流通过电阻性存储元件来产生数据电压。 产生参考电压，也可以基于产生的负载电压，并通过将从恒定电流反射的参考电流通过参考单元。 存储在电阻性存储器元件中的逻辑值基于数据电压和参考电压的比较来确定，其中确定不受处理电压 - 温度变化的影响。

    Offset canceling dual stage sensing circuit
    7.
    发明授权
    Offset canceling dual stage sensing circuit 有权
    偏移消除双级感测电路

    公开(公告)号：US09165630B2

    公开(公告)日：2015-10-20

    申请号：US14015845

    申请日：2013-08-30

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation

    Inventor： Seong-Ook Jung ,  Taehui Na ,  Jisu Kim ,  Jung Pill Kim ,  Seung Hyuk Kang

    IPC: G11C11/00 ,  G11C11/16 ,  G11C7/06 ,  G11C13/00

    CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C7/065 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2013/0057

    Abstract: An offset canceling dual stage sensing method includes sensing a data value of a resistive memory data cell using a first load PMOS gate voltage generated by a reference value of a resistive memory reference cell in a first stage operation. The method also includes sensing the reference value of the resistive memory reference cell using a second load PMOS gate voltage generated by the data value of the resistive memory data cell in a second stage operation of the resistive memory sensing circuit. By adjusting the operating point of the reference cell sensing, an offset canceling dual stage sensing circuit increases the sense margin significantly compared to that of a conventional sensing circuit.

    Abstract translation: 偏移消除双级感测方法包括：在第一级操作中使用由电阻性存储器参考单元的参考值产生的第一负载PMOS栅极电压来感测电阻性存储器数据单元的数据值。 该方法还包括使用在电阻性存储器感测电路的第二级操作中由电阻性存储器数据单元的数据值产生的第二负载PMOS栅极电压来感测电阻性存储器参考单元的参考值。 通过调整参考单元感测的工作点，与常规感测电路相比，偏移消除双级感测电路显着增加了感测余量。

    LATCHING CIRCUIT
    8.
    发明申请
    LATCHING CIRCUIT 有权
    锁定电路

    公开(公告)号：US20130182500A1

    公开(公告)日：2013-07-18

    申请号：US13785338

    申请日：2013-03-05

    Applicant: QUALCOMM Incorporated ,  Industry-Academic Cooperation Foundation, Yonsei University

    Inventor： Seong-Ook Jung ,  Kyungho Ryu ,  Jisu Kim ,  Jung Pill Kim ,  Seung H. Kang

    IPC: G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/1659 ,  G11C11/1673 ,  G11C13/0002 ,  G11C14/009

    Abstract: A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the resistance-based memory element at a first operating point of the sensing circuit.

    Abstract translation: 非易失性锁存电路包括一对交叉耦合的反相器，一对基于电阻的存储器元件和被配置为将数据写入到该对基于电阻的存储器元件的写入电路。 在锁定操作期间，一对基于电阻的存储器元件与一对交叉耦合的反相器隔离。 感测电路包括第一电流路径，其包括基于电阻的存储元件和感测电路的输出。 感测电路包括第二电流路径，以减小在感测电路的第一工作点处通过基于电阻的存储元件的电流。

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