公开(公告)号：US11955169B2

公开(公告)日：2024-04-09

申请号：US17210230

申请日：2021-03-23

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: A multi-port memory is provided that supports collision between a read port and a write port to the same multi-port bitcell. A sense amplifier reads a data bit from a multi-port bitcell when a write port to the multi-port bitcell is addressed during a system clock signal. Should a read port to the multi-port bitcell be addressed during the same system clock signal, a multiplexer selects for an output bit from the sense amplifier.

公开(公告)号：US11152921B1

公开(公告)日：2021-10-19

申请号：US17204421

申请日：2021-03-17

Applicant: QUALCOMM Incorporated

Inventor： Veerabhadra Rao Boda ,  Rahul Sahu ,  Sharad Kumar Gupta

IPC: H03K3/00 ,  H03K3/037 ,  H03K5/14 ,  H03K19/20 ,  H03K3/286 ,  H03K3/356

Abstract: Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.

公开(公告)号：US11049552B1

公开(公告)日：2021-06-29

申请号：US16827959

申请日：2020-03-24

Applicant: QUALCOMM Incorporated

Inventor： Pradeep Raj ,  Rahul Sahu ,  Sharad Kumar Gupta ,  Chulmin Jung

IPC: G11C7/12 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/4097 ,  G11C7/10 ,  G11C11/412 ,  G11C11/419

Abstract: Certain aspects of the present disclosure are directed to a memory circuit. The memory circuit generally includes a memory cell coupled between a bit-line and a complementary bit-line. The memory circuit also includes a first n-type metal-oxide-semiconductor (NMOS) transistor configured to couple the bit-line to a write drive input during a write cycle of the memory circuit. The memory circuit also includes a second NMOS transistor configured to couple the complementary bit-line to a complementary write drive input during the write cycle, and a multiplexer circuit having a first p-type metal-oxide-semiconductor (PMOS) transistor coupled between a voltage rail and the bit-line or the complementary bit-line, the multiplexer circuit being configured to couple, via the first PMOS transistor, the bit-line or the complementary bit-line to the voltage rail during the write cycle.

公开(公告)号：US10811086B1

公开(公告)日：2020-10-20

申请号：US16523350

申请日：2019-07-26

Applicant: QUALCOMM Incorporated

Inventor： Shiba Narayan Mohanty ,  Sharad Kumar Gupta ,  Rahul Sahu ,  Pradeep Raj ,  Veerabhadra Rao Boda ,  Adithya Bhaskaran ,  Akshdeepika

IPC: G11C11/00 ,  G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

公开(公告)号：US09928898B2

公开(公告)日：2018-03-27

申请号：US15085942

申请日：2016-03-30

Applicant: QUALCOMM Incorporated

Inventor： Rahul Sahu ,  Sharad Kumar Gupta

IPC: G11C16/08 ,  G11C11/419 ,  G11C11/412 ,  G11C11/418 ,  G11C8/08 ,  G11C11/413 ,  G11C16/30

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C11/412 ,  G11C11/413 ,  G11C11/418 ,  G11C16/08 ,  G11C16/30

Abstract: A memory and a method for operating a memory are provided. The memory includes a memory cell having a transistor and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline to compensate for a parameter of the transistor. The method includes asserting a wordline voltage to access a memory cell having a transistor and adjusting the wordline voltage to compensate for a parameter of the transistor. Another memory is provided. The memory includes a memory cell and a wordline driver outputting a wordline coupled to the memory cell. The wordline driver adjusts a voltage level of the wordline based on a feedback of the wordline.

公开(公告)号：US09837144B1

公开(公告)日：2017-12-05

申请号：US15408086

申请日：2017-01-17

Applicant: QUALCOMM Incorporated

Inventor： Rakesh Kumar Sinha ,  Mukund Narasimhan ,  Sharad Kumar Gupta

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C7/1009 ,  G11C7/1096 ,  G11C7/12

Abstract: A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.