-
21.发明授权Printed circuit board processor card for upgrading a processor-based system 失效用于升级基于处理器的系统的印刷电路板处理器卡
公开(公告)号：US5644760A
公开(公告)日：1997-07-01
申请号：US432906
申请日：1995-05-01
CPC分类号： G06F13/4068
摘要： A printed circuit board (PCB) processor card is described. The processor card includes a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus. The processor card is designed to include the elements that are most likely to be upgraded, i.e. the processor and the clock. As such it is particularly useful when employed for system upgrades.
摘要翻译： 描述了印刷电路板（PCB）处理器卡。 处理器卡包括处理器，其相关联的处理器卡系统总线，时钟发生器及其相关联的处理器卡系统时钟总线。 处理器卡被设计为包括最有可能升级的元件，即处理器和时钟。 因此，当用于系统升级时，它特别有用。
-
22.发明授权Method and apparatus for interfacing a system control unit for a multi-processor 失效用于连接多处理器的系统控制单元的方法和装置
公开(公告)号：US4965793A
公开(公告)日：1990-10-23
申请号：US306862
申请日：1989-02-03
申请人： R. Stephen Polzin , Roger G. Niles , Rueysen Lin
发明人： R. Stephen Polzin , Roger G. Niles , Rueysen Lin
IPC分类号： G06F13/12
CPC分类号： G06F13/122
摘要： To interface a system control unit with an input/unit in a computer system, an interface includes a transmitter for sequentially transmitting data packets and parity signals between the system control unit and the input/output unit, and a receiver for sequentially receiving the data packets and parity signals. The receiver includes a buffer for storing a plurality of the data packets. The stored data packets are controllably unloaded from the buffer, and a buffer emptied signal is sent back to the transmitter as each data packet is unloaded. The transmitter has a counter which calculates the number of data packets stored in the buffer and asserts a signal that prevents the transmitter from transmitting additional data packets when the buffer becomes full. The receiver compares the parity of the received data packets to the respective parity signals to check for parity errors. The receiver sends an acknowledge signal back to the transmitter in the absence of a parity error, and sends a retry signal back to the transmitter in the presence of a parity error. Preferably the data packets are transmitted along with a separate transmitter clock signal and respective command available signals, and the returned signals are sent back to the transmitter with a separate receiver clock signal, to permit synchronous reception of the data packets or returned signals. Respective data synchronizers in the transmitter and receiver eliminate the effect of skew between the transmitter and receiver clock signals.
-
公开(公告)号：US08611127B1
公开(公告)日：2013-12-17
申请号：US13495540
申请日：2012-06-13
IPC分类号： G11C5/06
CPC分类号： G11C5/02 , G11C5/066 , G11C7/1012 , G11C7/1045 , G11C7/106
摘要： A memory device having a scalable bandwidth I/O data bus includes a semiconductor die having a substrate with a first and a second surface. The substrate includes contact pads arranged in rows across the first surface and across the second surface. The contact pads on one surface may be physically arranged in vertical alignment with a corresponding contact pad on the other surface and may be electrically coupled to the corresponding contact pad using a via. The substrate also includes a metallization layer formed on the second surface. The metallization layer includes external data contact pads each arranged in vertical alignment with a respective contact pad on the second surface. Each row of contact pads may be grouped, and the external contact pads within a group are electrically coupled to an adjacent contact pad on the second surface by effectively logically shifting them to the right one contact pad.
摘要翻译： 具有可扩展带宽I / O数据总线的存储器件包括具有第一和第二表面的衬底的半导体管芯。 衬底包括跨越第一表面排列成跨越第二表面的接触焊盘。 一个表面上的接触焊盘可以物理地布置成与另一表面上的对应接触焊盘垂直对准，并且可以使用通孔电耦合到对应的接触焊盘。 基板还包括形成在第二表面上的金属化层。 金属化层包括每个与第二表面上的相应接触焊盘垂直对准布置的外部数据接触焊盘。 每一排接触焊盘可以被分组，并且组内的外部接触焊盘通过有效地逻辑地将它们移动到右一个接触焊盘而电耦合到第二表面上的相邻接触焊盘。
-
24.发明授权Mechanism for remotely accessing a portable computer including wireless communication functionality 有权用于远程访问便携式计算机的机制，包括无线通信功能公开(公告)号：US07890138B2
公开(公告)日：2011-02-15
申请号：US11478771
申请日：2006-06-30
IPC分类号： H04B1/38
CPC分类号： H04L63/102 , G06F21/43 , G06F2221/2101 , H04L51/00
摘要： A portable computer system such as a laptop computer system includes a computing subsystem that includes a processor that may execute instructions that implement application software, and a storage coupled to the processor that may store information. The laptop computer system also includes a wireless subsystem that may communicate with a wireless network. In addition, the wireless subsystem may receive an incoming communication and determine whether a requesting user is an authorized user. The processor may retrieve at least a portion of the information from the storage and send the retrieved information to a destination via email, for example, in response to a request by the requesting user for the information.
摘要翻译： 诸如膝上型计算机系统的便携式计算机系统包括计算子系统，其包括可以执行实现应用软件的指令的处理器，以及耦合到可存储信息的处理器的存储器。 膝上型计算机系统还包括可与无线网络通信的无线子系统。 此外，无线子系统可以接收传入通信并确定请求用户是否是授权用户。 处理器可以从存储器检索信息的至少一部分，并且例如响应于请求用户对该信息的请求，通过电子邮件将检索到的信息发送到目的地。
-
公开(公告)号：US07729465B2
公开(公告)日：2010-06-01
申请号：US11368785
申请日：2006-03-06
CPC分类号： H04L1/0026 , H04L1/0061 , H04L1/205 , H04L1/243 , H04L25/03006 , H04L2001/0094
摘要： A system including asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the slave device via a plurality of bidirectional data paths, for example. The master device may control data transfer between the master device and the slave device. More particularly, the master device may adaptively modify transmit characteristics subsequent to adaptively modifying receiver characteristics based upon information received from the slave device via one or more unidirectional data paths.
摘要翻译： 包括高速双向信令的不对称控制的系统包括例如从属设备和通过多个双向数据路径耦合到从设备的主设备。 主设备可以控制主设备和从设备之间的数据传输。 更具体地，主设备可以基于经由一个或多个单向数据路径从从设备接收到的信息自适应地修改接收机特性。
-
26.发明授权System including a host connected to a plurality of memory modules via a serial memory interconnect 有权系统包括通过串行存储器互连连接到多个存储器模块的主机公开(公告)号：US07421525B2
公开(公告)日：2008-09-02
申请号：US10842296
申请日：2004-05-10
申请人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
发明人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
CPC分类号： G06F13/4243 , G06F12/0215 , G06F12/0862 , G06F13/1626 , G06F2212/6022
摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
摘要翻译： 一种系统，包括耦合到串行连接的存储器模块链的主机。 在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控制集线器。 存储器模块通过多个存储器链路串联地连接到主机。 每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。 上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。 存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。
-
27.发明申请Platform security for a portable computer system including wireless functionality 审中-公开便携式计算机系统的平台安全性，包括无线功能公开(公告)号：US20080005783A1
公开(公告)日：2008-01-03
申请号：US11478739
申请日：2006-06-30
申请人： R. Stephen Polzin , Robert Ober
发明人： R. Stephen Polzin , Robert Ober
CPC分类号： H04L9/3271 , H04L9/3247 , H04L63/0853 , H04L2209/80 , H04W4/029 , H04W12/06 , H04W12/0802 , H04W12/1206
摘要： A portable computer system such as a laptop computer system includes a processor coupled to a wireless module that may communicate with a computer network via a connection to a wireless network. In addition, portable computer system includes an authentication unit that may be coupled to the wireless module and configured to generate and provide authentication information to the wireless module. The wireless module may be further configured to provide the authentication information to the computer network in response to a challenge from the computer network during a initiation of the connection to the computer network without intervention of the processor. In addition, the wireless module may enable features such as authenticating a remote admin-level user, which may further enable that user to perform security related functions through the wireless module.
摘要翻译： 诸如膝上型计算机系统的便携式计算机系统包括耦合到无线模块的处理器，其可以经由到无线网络的连接与计算机网络通信。 此外，便携式计算机系统包括可以耦合到无线模块并被配置为生成并向无线模块提供认证信息的认证单元。 无线模块还可以被配置为在开始与计算机网络的连接之间响应于来自计算机网络的挑战而向计算机网络提供认证信息，而无需处理器的干预。 此外，无线模块可以启用诸如认证远程管理级用户的特征，这可以进一步使该用户通过无线模块执行与安全相关的功能。
-
公开(公告)号：US5909571A
公开(公告)日：1999-06-01
申请号：US699169
申请日：1996-08-19
CPC分类号： G06F1/10
摘要： The clock configuration of a printed circuit board (PCB) processor card is described. A processor card including a processor, its associated processor card system bus, a clock generator, and its associated processor card system clock bus is optimized by providing various clock configurations and distributions. In one configuration, multiple clock signals are coupled to a system clock bus for distributing to a host card having system devices. In another configuration, multiple clock signals having various clock rates are coupled to the processor device on the processor card.
摘要翻译： 描述印刷电路板（PCB）处理器卡的时钟配置。 通过提供各种时钟配置和分布来优化包括处理器，其相关联的处理器卡系统总线，时钟发生器及其相关联的处理器卡系统时钟总线的处理器卡。 在一种配置中，多个时钟信号耦合到系统时钟总线，用于分配到具有系统设备的主机卡。 在另一种配置中，具有各种时钟速率的多个时钟信号被耦合到处理器卡上的处理器设备。
-
公开(公告)号：US5680297A
公开(公告)日：1997-10-21
申请号：US511640
申请日：1995-08-07
CPC分类号： G06F1/182 , H05K9/0064 , H05K1/0216 , H05K1/14
摘要： A computer system connector panel including EMI filtering on the computer system housing connector panel instead of on the system motherboard so that I/O signals are filtered just before being transmitted out of the computer system housing thereby reducing EMI affects on external A/V devices.
摘要翻译： 计算机系统连接器面板包括计算机系统外壳连接器面板上的EMI滤波，而不是在系统主板上，以便在传出计算机系统外壳之前对I / O信号进行滤波，从而降低EMI对外部A / V设备的影响。
-
公开(公告)号：US5592631A
公开(公告)日：1997-01-07
申请号：US432620
申请日：1995-05-02
申请人： James D. Kelly , R. Stephen Polzin
发明人： James D. Kelly , R. Stephen Polzin
IPC分类号： G06F13/364 , G06F13/366
CPC分类号： G06F13/364
摘要： The present invention, generally speaking, provides a system and method of decoupling the address and data buses of a system bus using side band information signals. A computer system with which the invention may be used has a system bus including an address bus and a data bus and has, operatively connected to said system bus, multiple master devices, including a microprocessor, and multiple slave devices. In accordance with one embodiment of the invention, the address bus and the data bus are decoupled by providing, in addition to signals carried by the system bus, first side-band signals including, for each master device besides the microprocessor, an address arbitration signal, and providing, in addition to signals carried by the system bus, second side-band signals including, for each slave device, an address termination signal, a data arbitration signal, and a read-ready signal indicating that a respective slave device has data to present on the system bus. An address arbitration vector is formed, composed of address arbitration signals for the master devices, an address termination vector is formed, composed of address termination signals for the slave devices, and a read-ready vector is formed, composed of read-ready signals for the slave devices. The address arbitration vector and the address termination vector are sampled. Using a queue structure having a front and a rear, pairs of address arbitration and address termination vectors sampled at different sampling times are queued. Given a pair of address arbitration and address termination vectors at the head of the queue structure and a subsequent, corresponding read-ready vector, a data arbitration signal is issued to one of the slave devices and one of the master devices, as a "paired data bus grant."
摘要翻译： 本发明一般地提供了一种使用边带信息信号去除系统总线的地址和数据总线的系统和方法。 可以使用本发明的计算机系统具有包括地址总线和数据总线的系统总线，并且具有可操作地连接到所述系统总线的多个主设备，包括微处理器和多个从设备。 根据本发明的一个实施例，地址总线和数据总线除了由系统总线携带的信号之外还提供第一边带信号，除了微处理器之外还包括每个主设备的地址仲裁信号 并且除了由系统总线承载的信号之外，还提供第二边带信号，包括针对每个从设备的地址终止信号，数据仲裁信号和指示相应从设备具有数据的可读准备信号 在系统总线上呈现。 形成地址仲裁向量，由主设备的地址仲裁信号组成，形成地址终止向量，由从设备的地址终止信号组成，并且形成就绪向量，其包括用于 从设备。 对地址仲裁向量和地址终止向量进行采样。 使用具有前端和后端的队列结构，对在不同采样时间采样的地址仲裁和地址终止矢量进行排队。 给定在队列结构的头部的一对地址仲裁和地址终止向量以及随后的对应的可读向量，向其中一个从设备和一个主设备发出数据仲裁信号作为“配对 数据总线授权。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.02 秒)