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公开(公告)号：US08218347B1
公开(公告)日：2012-07-10
申请号：US12902599
申请日：2010-10-12
IPC分类号： G11C5/06
CPC分类号： G11C5/02 , G11C5/066 , G11C7/1012 , G11C7/1045 , G11C7/106
摘要： A memory device having a scalable bandwidth I/O data bus includes a semiconductor die having a substrate with a first and a second surface. The substrate includes contact pads arranged in rows across the first surface and across the second surface. The contact pads on one surface may be physically arranged in vertical alignment with a corresponding contact pad on the other surface and may be electrically coupled to the corresponding contact pad using a via. The substrate also includes a metallization layer formed on the second surface. The metallization layer includes external data contact pads each arranged in vertical alignment with a respective contact pad on the second surface. Each row of contact pads may be grouped, and the external contact pads within a group are electrically coupled to an adjacent contact pad on the second surface by effectively logically shifting to them to right one contact pad.
摘要翻译： 具有可扩展带宽I / O数据总线的存储器件包括具有第一和第二表面的衬底的半导体管芯。 衬底包括跨越第一表面排列成跨越第二表面的接触焊盘。 一个表面上的接触焊盘可以物理地布置成与另一表面上的对应接触焊盘垂直对准，并且可以使用通孔电耦合到对应的接触焊盘。 基板还包括形成在第二表面上的金属化层。 金属化层包括每个与第二表面上的相应接触焊盘垂直对准布置的外部数据接触焊盘。 每一排接触焊盘可以被分组，并且组内的外部接触焊盘通过有效地逻辑地转移到右侧的一个接触焊盘而电耦合到第二表面上的相邻接触焊盘。
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公开(公告)号：US08611127B1
公开(公告)日：2013-12-17
申请号：US13495540
申请日：2012-06-13
IPC分类号： G11C5/06
CPC分类号： G11C5/02 , G11C5/066 , G11C7/1012 , G11C7/1045 , G11C7/106
摘要： A memory device having a scalable bandwidth I/O data bus includes a semiconductor die having a substrate with a first and a second surface. The substrate includes contact pads arranged in rows across the first surface and across the second surface. The contact pads on one surface may be physically arranged in vertical alignment with a corresponding contact pad on the other surface and may be electrically coupled to the corresponding contact pad using a via. The substrate also includes a metallization layer formed on the second surface. The metallization layer includes external data contact pads each arranged in vertical alignment with a respective contact pad on the second surface. Each row of contact pads may be grouped, and the external contact pads within a group are electrically coupled to an adjacent contact pad on the second surface by effectively logically shifting them to the right one contact pad.
摘要翻译： 具有可扩展带宽I / O数据总线的存储器件包括具有第一和第二表面的衬底的半导体管芯。 衬底包括跨越第一表面排列成跨越第二表面的接触焊盘。 一个表面上的接触焊盘可以物理地布置成与另一表面上的对应接触焊盘垂直对准，并且可以使用通孔电耦合到对应的接触焊盘。 基板还包括形成在第二表面上的金属化层。 金属化层包括每个与第二表面上的相应接触焊盘垂直对准布置的外部数据接触焊盘。 每一排接触焊盘可以被分组，并且组内的外部接触焊盘通过有效地逻辑地将它们移动到右一个接触焊盘而电耦合到第二表面上的相邻接触焊盘。
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公开(公告)号：US08533403B1
公开(公告)日：2013-09-10
申请号：US12895036
申请日：2010-09-30
申请人： Patrick Y. Law
发明人： Patrick Y. Law
IPC分类号： G06F13/37
CPC分类号： G06F13/1605 , G06F13/1684 , Y02D10/14
摘要： Techniques are disclosed relating to maximizing utilization of memory systems within power constraints of the memory systems. In one embodiment, an integrated circuit may include multiple memory controllers and an arbitration unit. Each memory controller may be configured to generate requests to perform memory operations on one or more portions of memory. The arbitration unit may be configured to grant no more than a specified number of requests during a time window TW. In some embodiments, a voltage converter that supplies power to the memory system may be configured to supply power to perform no more than the specified number of requests during the time window TW. The arbitration unit may thus be used, in some embodiments, to ensure that the greatest possible number of the specified number of memory requests are granted during a given time window TW (without exceeding the specified number).
摘要翻译： 公开了关于在存储器系统的功率限制内最大化存储器系统的利用率的技术。 在一个实施例中，集成电路可以包括多个存储器控制器和仲裁单元。 每个存储器控制器可以被配置为产生对存储器的一个或多个部分执行存储器操作的请求。 仲裁单元可以被配置为在时间窗口TW期间授予不超过指定数量的请求。 在一些实施例中，向存储器系统供电的电压转换器可被配置为在时间窗口TW期间提供功率以执行不超过指定数量的请求。 因此，在一些实施例中，可以使用仲裁单元来确保在给定的时间窗口TW（不超过指定的数量）期间授予最大可能数量的指定数量的存储器请求。
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公开(公告)号：US08924752B1
公开(公告)日：2014-12-30
申请号：US13090459
申请日：2011-04-20
申请人： Patrick Y. Law , Robert A. Drebin , Keith Cox , James S. Ismail
发明人： Patrick Y. Law , Robert A. Drebin , Keith Cox , James S. Ismail
IPC分类号： G06F1/00
CPC分类号： G06F1/3206 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/172
摘要： In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.
摘要翻译： 在一个实施例中，系统包括控制处理器管理电力的占空比的电源管理控制。 占空比可以是处理器上电的时间量占总时间的百分比。 通过在一段时间内频繁地加电和断电处理器，可以控制处理器的功耗，同时提供处理器持续可用的感知。 例如，处理器可以是图形处理单元（GPU），并且管理占空比的时间段可以是要在系统的用户观看的显示屏上显示的帧。
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公开(公告)号：US06664958B1
公开(公告)日：2003-12-16
申请号：US09722378
申请日：2000-11-28
申请人： Mark M. Leather , Anthony P. DeLaurier , Patrick Y. Law , Robert A. Drebin , Howard Cheng , Robert Moore
发明人： Mark M. Leather , Anthony P. DeLaurier , Patrick Y. Law , Robert A. Drebin , Howard Cheng , Robert Moore
IPC分类号： G06T1540
摘要： A graphics system including a custom graphics and audio processor produces exciting 2D and 3D graphics and surround sound. The system includes a graphics and audio processor including a 3D graphics pipeline and an audio digital signal processor. The same texture mapping hardware used for color texturing provides resampled z texturing for sprites with depth or other applications. A z blender performs a z blending operation in screen space to blend surface z values with z texel values to provide per-pixel mapping of resampled z textures onto sampled 3D surface locations. Z texels can represent absolute depths or depth displacements relative to primitive surface depth. The z texel values may add to or replace primitive surface z values, and a constant bias may be added if desired. The resulting depth values are used for occlusion testing. Z textures can be generated by copying out portions of an embedded z buffer and providing the copied depth values to the texture mapping hardware. Multiple z texel formats are supported.
摘要翻译： 包括定制图形和音频处理器的图形系统产生令人兴奋的2D和3D图形和环绕声。 该系统包括包括3D图形流水线和音频数字信号处理器的图形和音频处理器。 用于颜色纹理的相同纹理映射硬件为深度或其他应用的精灵提供了重新采样的z纹理。 z混合器在屏幕空间中执行z混合操作，以将表面z值与z纹素值混合，以将采样的z纹理的每像素映射提供到采样的3D表面位置。 Z纹理可以表示相对于原始表面深度的绝对深度或深度位移。 z纹理值可以添加或替换原始表面z值，并且如果需要，可以添加恒定偏差。 所得到的深度值用于遮挡测试。 可以通过复制嵌入的z缓冲区的部分并将复制的深度值提供给纹理映射硬件来生成Z纹理。 支持多种z纹理格式。
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6.发明授权
公开(公告)号：US5638533A
公开(公告)日：1997-06-10
申请号：US542191
申请日：1995-10-12
申请人： Patrick Y. Law
发明人： Patrick Y. Law
CPC分类号： H04N5/14 , G11C7/1006 , G11C7/1075
摘要： A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the data values into the correct order, if necessary, and provides the retrieved data values to the processing array. The select logic and shift network preferably include arrays of multiplexers. In particular, the select logic preferably includes an array of n 2:1 multiplexers, and the shift network preferably comprises an array of n.times.n:1 multiplexers. In an alternative embodiment, the shift network includes multiple stages of arrays of multiplexers. A data register according to the present invention is particularly advantageous for video applications requiring a fast data path, where the data values are 8-bit pixels.
摘要翻译： 用于向n元素并行处理阵列提供数据值的数据寄存器包括具有第一和第二存储器模块的存储器缓冲器，其中每个模块包括n列数据值。 地址解码器从存储器模块接收一次访问n个数据值的地址，并且断言地址值以访问第一和第二存储器模块的相应行。 选择逻辑在第一和第二存储器模块的相应列之间进行选择以根据预定顺序检索所需的数据值。 如果需要，移位网络将数据值重新排列成正确的顺序，并将检索的数据值提供给处理阵列。 选择逻辑和移位网络优选地包括多路复用器阵列。 特别地，选择逻辑优选地包括n 2：1多路复用器的阵列，并且移位网络优选地包括n×n：1个多路复用器的阵列。 在替代实施例中，移位网络包括多级多路复用器阵列。 根据本发明的数据寄存器对于需要快速数据路径的视频应用是特别有利的，其中数据值是8位像素。
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公开(公告)号：US09652560B1
公开(公告)日：2017-05-16
申请号：US13314005
申请日：2011-12-07
申请人： James Wang , Robert A. Drebin , Patrick Y. Law
发明人： James Wang , Robert A. Drebin , Patrick Y. Law
CPC分类号： G06F17/30994 , G06F12/08 , G06F12/0893 , G06F12/1027 , G06F13/1668 , G06F2212/1016
摘要： Techniques are disclosed relating to handling page faults created by a processor unit. In some embodiments, such techniques may be used within the context of graphics processor units (GPUs) to reduce the chances that a page fault will result in a GPU-pipeline stall. In one embodiment, a processor includes a graphics processor pipeline and a memory management unit. The graphics processor pipeline includes a plurality of pipeline stages. The memory management unit is configured to determine that a first data request from a first of the plurality of pipeline stages causes a page fault, and to service requests from one or more others of the plurality of pipeline stages while the page fault is being serviced.
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公开(公告)号：US08000469B2
公开(公告)日：2011-08-16
申请号：US11650422
申请日：2007-01-08
申请人： Mark Buer , Patrick Y. Law , Zheng Qi
发明人： Mark Buer , Patrick Y. Law , Zheng Qi
IPC分类号： H04L9/00
CPC分类号： H04L9/0643 , H04L2209/125
摘要： Provided is an architecture (hardware implementation) for an authentication engine to increase the speed at which multi-loop and/or multi-round authentication algorithms may be performed on data packets transmitted over a computer network. Authentication engines in accordance with the present invention apply a variety of techniques that may include, in various applications, collapsing two multi-round authentication algorithm (e.g., SHA1 or MD5 or variants) processing rounds into one; reducing operational overhead by scheduling the additions required by a multi-round authentication algorithm in such a matter as to reduce the overall critical timing path (“hiding the ads”); and, for a multi-loop (e.g., HMAC) variant of a multi-round authentication algorithm, pipelining the inner and outer loops. In one particular example of applying the invention in an authentication engine using the HMAC-SHA1 algorithm of the IPSec protocol, collapsing of the conventional 80 SHA1 rounds into 40 rounds, hiding the ads, and pipelining the inner and outer loops allows HMAC-SHA1 to be conducted in approximately the same time as conventional SHA1.
摘要翻译： 提供了一种用于认证引擎来提高可以对通过计算机网络传输的数据分组执行多循环和/或多轮认证算法的速度的架构（硬件实现）。 根据本发明的认证引擎应用各种技术，其可以在各种应用中包括将两个多轮验证算法（例如，SHA1或MD5或变体）合并成一个; 通过调度多轮认证算法所需的添加来减少总体关键时序路径（“隐藏广告”），从而减少运营开销; 并且对于多循环（例如，HMAC）变体的多轮认证算法，流水线化内圈和外循环。 在使用IPSec协议的HMAC-SHA1算法的认证引擎中应用本发明的一个具体示例中，将常规80个SHA1回合折叠成40个回合，隐藏广告并且流水线化内部和外部循环允许HMAC-SHA1 在与传统SHA1大致相同的时间内进行。
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公开(公告)号：US6091425A
公开(公告)日：2000-07-18
申请号：US24828
申请日：1998-02-17
申请人： Patrick Y. Law
发明人： Patrick Y. Law
CPC分类号： G06T1/00
摘要： In a computer, a graphics system and process for generating a multisample image coverage mask comprising a constant number of samples. The mask covers an array of pixels with each pixel containing a number of samples. The samples are associated with information regarding the image which is used by the computer graphics system to render the image on a pixel. The samples utilized in creating the mask are those closest to the center of an image.
摘要翻译： 在计算机中，用于生成包含常数样本的多采样图像覆盖掩模的图形系统和处理。 掩模覆盖像素阵列，每个像素包含多个样本。 样本与由计算机图形系统用于在像素上渲染图像的图像的信息相关联。 用于创建掩模的样品是最接近图像中心的样品。
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公开(公告)号：US09390461B1
公开(公告)日：2016-07-12
申请号：US13466597
申请日：2012-05-08
申请人： Jason P. Jane , Richard W. Schreyer , Michael J. E. Swift , Gokhan Avkarogullari , Luc R. Semeria , Patrick Y. Law
发明人： Jason P. Jane , Richard W. Schreyer , Michael J. E. Swift , Gokhan Avkarogullari , Luc R. Semeria , Patrick Y. Law
CPC分类号： G06F1/3287 , G06F1/28 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/3246 , G06F9/30145 , G06F9/442 , G06T1/20 , G06T2200/28
摘要： In one embodiment, a system controls a duty cycle of a processor (e.g. a graphics processing unit (GPU)) to manage power. The GPU may include a snoop indicator that may control whether or not the GPU captures and/or responds to communications from another processor (e.g. a central processing unit (CPU) that executes a driver associate with the GPU). A snooze indicator may control whether or not the GPU is automatically repowered at the start of the next frame, or is repowered only if the communication indicating additional work has been received. In an embodiment, the GPU mode controls discussed above may permit the GPU firmware executed with the GPU itself to control duty cycle power down, independent of the driver executing on the CPU.
摘要翻译： 在一个实施例中，系统控制处理器（例如，图形处理单元（GPU））的占空比以管理功率。 GPU可以包括窥探指示器，其可以控制GPU是否捕获和/或响应来自另一个处理器（例如，执行与GPU相关联的驱动程序的驱动程序的中央处理单元（CPU））的通信。 打盹指示器可以控制GPU是否在下一帧的开始时自动地被重新供电，或者仅当已经接收到指示附加的工作的通信时被重新供电。 在一个实施例中，上面讨论的GPU模式控制可以允许GPU本身执行的GPU固件控制占空比功率下降，而与在CPU上执行的驱动程序无关。
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