公开(公告)号：US20210358535A1

公开(公告)日：2021-11-18

申请号：US17341048

申请日：2021-06-07

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US10665289B2

公开(公告)日：2020-05-26

申请号：US16032633

申请日：2018-07-11

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/3237 ,  G06F1/04 ,  G06F1/3234 ,  G06F1/08 ,  G11C11/408

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US10607670B2

公开(公告)日：2020-03-31

申请号：US15794177

申请日：2017-10-26

Applicant: Rambus Inc.

Inventor： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC: G06F12/00 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

公开(公告)号：US09704560B2

公开(公告)日：2017-07-11

申请号：US15242423

申请日：2016-08-19

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/32 ,  G06F1/04 ,  G06F1/08 ,  G11C11/408

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US09684321B2

公开(公告)日：2017-06-20

申请号：US14699780

申请日：2015-04-29

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Michael D. Bucher ,  Lei Luo ,  Chaofeng Charlie Huang ,  Amir Amirkhany ,  Huy M. Nguyen ,  Hsuan-Jung (Bruce) Su ,  John Wilson

IPC: G05F1/10 ,  G05F1/46 ,  G11C5/14

CPC classification number: G05F1/462 ,  G11C5/147

Abstract: An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

公开(公告)号：US09430027B2

公开(公告)日：2016-08-30

申请号：US14799362

申请日：2015-07-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lei Luo ,  Liji Gopalakrishnan

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F1/32 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G06F1/04

CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/3237 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/22 ,  G11C11/4072 ,  G11C11/4074 ,  G11C11/4087 ,  G11C11/4096 ,  Y02D10/128 ,  Y02D50/20

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

公开(公告)号：US09294317B1

公开(公告)日：2016-03-22

申请号：US13831993

申请日：2013-03-15

Applicant: Rambus Inc.

Inventor： John Wilson ,  Lei Luo ,  Wayne D. Dettloff

IPC: H04L25/03

CPC classification number: H04L25/03878 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/03012 ,  H04L25/03343

Abstract: AC-coupled termination and equalization, including transmit equalization and/or receive equalization, are combined to create a high bandwidth channel that requires no special coding and consumes no or negligible DC current.

Abstract translation: 包括发射均衡和/或接收均衡在内的AC耦合终端和均衡被组合以产生不需要特殊编码并且消耗不可忽略的DC电流的高带宽信道。

公开(公告)号：US09148187B2

公开(公告)日：2015-09-29

申请号：US13944501

申请日：2013-07-17

Applicant: Rambus Inc.

Inventor： Michael Bucher ,  Lei Luo

IPC: H04B3/46 ,  H04B1/16

CPC classification number: H04B1/16 ,  H04L25/08

Abstract: A single-ended receiver compares signal levels representing current symbols to levels representing immediately preceding symbols to resolve the symbols. The receiver applies offsets selected based on resolved prior symbols to interpret successive like-symbols.

Abstract translation: 单端接收器将表示当前符号的信号电平与表示紧接在前的符号的电平进行比较，以解析符号。 接收机应用基于解析的先前符号选择的偏移来解释连续的相似符号。

公开(公告)号：US08867595B1

公开(公告)日：2014-10-21

申请号：US13913743

申请日：2013-06-10

Applicant: Rambus Inc.

Inventor： Lei Luo ,  Barry W. Daly ,  Kambiz Kaviani ,  John Cronan Eble, III ,  John Wilson

IPC: H04B17/00 ,  H03K3/013

CPC classification number: H03K3/013 ,  G11C5/147 ,  G11C29/021 ,  G11C29/022 ,  G11C29/028 ,  H04L25/0296 ,  H04L25/06 ,  H04L25/08

Abstract: A signal on a transmitter tracks noise on a ground node in a manner decoupled from a positive node of a power supply. The signal is transmitted from the transmitter to the receiver. A reference voltage is generated on the receiver to track noise on a ground node in the receiver. Consequently, the received signal and the reference voltage have substantially the same noise characteristics, which become common mode noise that can be cancelled out when these two signals are compared against each other. In a further embodiment, the reference voltage is compared against a predetermined calibration pattern. An error signal is generated based on a difference between the sampler output and the predetermined calibration pattern. The error signal is then used to adjust the reference voltage so that the DC level of the reference voltage is positioned substantially in the middle of the received signal.

Abstract translation: 发射机上的信号以与电源的正节点分离的方式跟踪接地节点上的噪声。 信号从发射机发射到接收机。 在接收机上产生参考电压以跟踪接收机中接地节点上的噪声。 因此，接收信号和参考电压具有基本上相同的噪声特性，这些噪声特性成为当这两个信号彼此进行比较时可以消除的共模噪声。 在另一实施例中，将参考电压与预定校准图案进行比较。 基于采样器输出和预定校准图案之间的差异产生误差信号。 然后使用误差信号来调整参考电压，使得参考电压的直流电平基本上位于接收信号的中间。

公开(公告)号：US20140036977A1

公开(公告)日：2014-02-06

申请号：US13944501

申请日：2013-07-17

Applicant: Rambus Inc.

Inventor： Michael Bucher ,  Lei Luo

IPC: H04B1/16

CPC classification number: H04B1/16 ,  H04L25/08

Abstract: A single-ended receiver compares signal levels representing current symbols to levels representing immediately preceding symbols to resolve the symbols. The receiver applies offsets selected based on resolved prior symbols to interpret successive like-symbols.

Abstract translation: 单端接收器将表示当前符号的信号电平与表示紧接在前的符号的电平进行比较，以解析符号。 接收机应用基于解析的先前符号选择的偏移来解释连续的相似符号。