公开(公告)号：US20140204111A1

公开(公告)日：2014-07-24

申请号：US14156722

申请日：2014-01-16

申请人： Karthik Vaidyanathan ,  Marco Salvi ,  Carl Jacob Munkberg ,  Franz Petrik Clarberg

发明人： Karthik Vaidyanathan ,  Marco Salvi ,  Carl Jacob Munkberg ,  Franz Petrik Clarberg

IPC分类号： G06T5/00

CPC分类号： G02B27/0075 ,  G02B27/46 ,  G06T5/002 ,  G06T11/00 ,  G06T15/503 ,  G06T2200/21

摘要： An algorithm may reconstruct defocus blur from a sparsely sampled light field. Light field samples are generated, using stochastic rasterization or ray tracing as examples. Then the samples are partitioned into depth layers. These depth layers are filtered independently and then combined together, taking into account inter-layer visibility. Since each layer corresponds to a smaller depth range, it results in more effective reconstruction filters than previous approaches.

摘要翻译： 算法可以从稀疏采样的光场重建散焦模糊。 使用随机光栅化或光线跟踪作为示例生成光场样本。 然后将样品分成深层。 这些深度层被独立过滤，然后结合在一起，考虑到层间可视性。 由于每个层对应于较小的深度范围，所以与先前的方法相比，其产生更有效的重构滤波器。

公开(公告)号：US20130271465A1

公开(公告)日：2013-10-17

申请号：US13992410

申请日：2011-12-30

申请人： Franz P. Clarberg ,  Robert M. Toth ,  Karthik Vaidyanathan

发明人： Franz P. Clarberg ,  Robert M. Toth ,  Karthik Vaidyanathan

IPC分类号： G06T15/80

CPC分类号： G06T15/80 ,  G06T15/005

摘要： A graphics pipeline combines the benefits of decoupling sampling with deferred shading. In the rasterization phase, a shading point is computed for each sample. After rasterization is finished, the shading points are sorted to extract coherence and groups of shading points shaded. This enables high sampling rates with efficient reuse of shading, in addition to other unique benefits.

摘要翻译： 图形管道结合了去耦采样与延迟着色的优点。 在光栅化阶段，为每个样本计算一个阴影点。 光栅化完成后，对阴影点进行排序，以提取相干性和遮蔽阴影组。 除了其他独特的优点之外，这样可以实现高采样率，同时有效地重用阴影。

公开(公告)号：US20130257885A1

公开(公告)日：2013-10-03

申请号：US13590490

申请日：2012-08-21

申请人： Karthik Vaidyanathan ,  Marco Salvi ,  Robert M. Toth ,  Aaron Lefohn

发明人： Karthik Vaidyanathan ,  Marco Salvi ,  Robert M. Toth ,  Aaron Lefohn

IPC分类号： G06T11/40

CPC分类号： G06T15/503 ,  G06T2210/12

摘要： The problem of generating high quality images with a rendering pipeline based on decoupled sampling may be addressed by generating non-extrapolated shading locations and by determining improved texture filtering footprints. This may be accomplished by performing shading at the center of a bounding box that bounds mapped shading samples.

摘要翻译： 可以通过生成非外推阴影位置并通过确定改进的纹理过滤占位面积来解决利用基于去耦取样的渲染流水线生成高质量图像的问题。 这可以通过在限制映射的阴影样本的边界框的中心处执行阴影来实现。

公开(公告)号：US08452830B2

公开(公告)日：2013-05-28

申请号：US12327395

申请日：2008-12-03

申请人： Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShekhar Ayyalasomayajula

发明人： Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShekhar Ayyalasomayajula

IPC分类号： G06F7/38

CPC分类号： G06F7/4818

摘要： A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

摘要翻译： CORDIC处理器具有多个级，每个级具有X输入，Y输入，符号输入，符号输出，X输出，Y输出，具有ROTATE或VECTOR值的模式控制输入，以及 每个CORDIC级具有通过移位Y输入k次而产生输出的第一移位，通过移位X个输入k次来产生输出的第二移位;当模式控制时，具有耦合到符号输入的输出的多路复用器 当模式输入为VECTOR时，输入为ROTATE和Y输入的符号，形成第一移位输出和多路复用器输出的乘积的第一乘法器，形成第二移位输出和反相多路复用器的乘积的第二乘法器 输出，从第一乘法器输出和X输入的和形成X输出的第一加法器和从第二乘法器输出和Y输入的和形成Y输出的第二加法器。

公开(公告)号：US08139699B2

公开(公告)日：2012-03-20

申请号：US12185688

申请日：2008-08-04

申请人： Karthik Vaidyanathan ,  Suryanarayana Varma Nallaparaju

发明人： Karthik Vaidyanathan ,  Suryanarayana Varma Nallaparaju

IPC分类号： H04L7/00

CPC分类号： H04L27/2647

摘要： A preamble detector for a plurality of streams of baseband digitized signals has a plurality of preamble processors, each preamble processor coupled to an input and generating an output. Each preamble processor has an input coupled to a first delay, the output of the first delay coupled to a second delay generating an output. The first and second delay are substantially equal to a preamble part. A first multiplier generates an output from a conjugated output of the second delay output and a first delay output. A second multiplier generates an output from a conjugated first delay output and an input stream. The first and second multiplier outputs are accumulated over an interval, and the complex output of the accumulator is formed into a magnitude, thereby generating the output of each preamble processor. The outputs of the preamble processors are summed and compared to a threshold to generate a preamble detect.

摘要翻译： 用于多个基带数字化信号流的前导码检测器具有多个前同步码处理器，每个前同步码处理器耦合到输入并产生输出。 每个前导处理器具有耦合到第一延迟的输入，第一延迟的输出耦合到产生输出的第二延迟。 第一和第二延迟基本上等于前导码部分。 第一乘法器产生来自第二延迟输出的共轭输出的输出和第一延迟输出。 第二乘法器产生来自共轭第一延迟输出和输入流的输出。 第一乘法器和第二乘法器输出在一个间隔上累积，并且累加器的复数输出形成一个幅度，由此产生每个前导码处理器的输出。 将前同步码处理器的输出相加并与阈值进行比较，以产生前导码检测。

公开(公告)号：US07844007B2

公开(公告)日：2010-11-30

申请号：US12146446

申请日：2008-06-26

申请人： Partha Sarathy Murali ,  Paul Rueuben Vincent ,  Karthik Vaidyanathan ,  Phanimithra Gangalakurti

发明人： Partha Sarathy Murali ,  Paul Rueuben Vincent ,  Karthik Vaidyanathan ,  Phanimithra Gangalakurti

IPC分类号： H04K1/10 ,  H04B17/02 ,  H04J11/00

CPC分类号： H04L27/2675 ,  H04L27/261 ,  H04L27/2659

摘要： A wireless signal processor for use in identifying a maximum Carrier to Noise Interference Ratio (CINR) associated with a plurality of received OFDMA subcarriers has a candidate generator for forming a plurality of candidate values from a particular set of received subcarriers by forming candidate values based on the received subcarriers in combination with possible integer preamble offsets and possible preamble values. A candidate evaluator selects which of the possible preamble values and integer frequency offset values have the maximum CINR, and provides the maximum CINR with IFO and preamble index as outputs.

摘要翻译： 用于识别与多个接收的OFDMA子载波相关联的最大载波与噪声干扰比（CINR）的无线信号处理器具有候选发生器，用于通过基于接收到的子载波的特定集合形成候选值，形成候选值 所接收的子载波与可能的整数前导码偏移和可能的前导码值组合。 候选评估器选择哪个可能的前导码值和整数频率偏移值具有最大CINR，并且将具有IFO和前导索引的最大CINR提供为输出。

公开(公告)号：US20100138631A1

公开(公告)日：2010-06-03

申请号：US12326196

申请日：2008-12-02

申请人： Phanimithra GANGALAKURTI ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShehar Ayyalasomayajula

发明人： Phanimithra GANGALAKURTI ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShehar Ayyalasomayajula

IPC分类号： G06F15/76 ,  G06F9/302

CPC分类号： G06F7/5446

摘要： A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

摘要翻译： CORDIC处理器具有多个级，每个级具有X输入，Y输入，符号输入，符号输出，X输出，Y输出，具有ROTATE或VECTOR值的模式控制输入，以及 每个CORDIC级具有通过移位Y输入k次而产生输出的第一移位，通过移位X个输入k次来产生输出的第二移位;当模式控制时，具有耦合到符号输入的输出的多路复用器 当模式输入为VECTOR时，输入为ROTATE和Y输入的符号，形成第一移位输出和多路复用器输出的乘积的第一乘法器，形成第二移位输出和反相多路复用器的乘积的第二乘法器 输出，从第一乘法器输出和X输入的和形成X输出的第一加法器和从第二乘法器输出和Y输入的和形成Y输出的第二加法器。

公开(公告)号：US20100131577A1

公开(公告)日：2010-05-27

申请号：US12324835

申请日：2008-11-27

申请人： Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShekhar Ayyalasomayajula

发明人： Phanimithra Gangalakurti ,  Karthik Vaidyanathan ,  Partha Sarathy Murali ,  InduShekhar Ayyalasomayajula

IPC分类号： G06F7/00

CPC分类号： G06F7/5446

摘要： A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.

摘要翻译： CORDIC处理器具有多个级，每个级具有X输入，Y输入，符号输入，符号输出，X输出，Y输出，具有ROTATE或VECTOR值的模式控制输入，以及 每个CORDIC级具有通过移位Y输入k次而产生输出的第一移位，通过移位X个输入k次来产生输出的第二移位;当模式控制时，具有耦合到符号输入的输出的多路复用器 当模式输入为VECTOR时，输入为ROTATE和Y输入的符号，形成第一移位输出和多路复用器输出的乘积的第一乘法器，形成第二移位输出和反相多路复用器的乘积的第二乘法器 输出，从第一乘法器输出和X输入的和形成X输出的第一加法器和从第二乘法器输出和Y输入的和形成Y输出的第二加法器。

公开(公告)号：US20100046646A1

公开(公告)日：2010-02-25

申请号：US12197230

申请日：2008-08-23

申请人： Prem Kiran NERELLA ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

发明人： Prem Kiran NERELLA ,  Karthik Vaidyanathan ,  Partha Sarathy Murali

IPC分类号： H04J11/00 ,  H04L27/28

CPC分类号： H04L27/2647 ,  H04L27/2626

摘要： A filter for receiver and operative on a stream of OFDM symbols has a symbol timing identifier which indicates the time interval for each symbol and also indicates a non-truncation interval and a truncation interval of the stream of symbols. The stream of OFDM symbols is applied to an infinite impulse response (IIR) filter with a reset input for resetting internal registers such that during the non-truncation interval, the reset input is not asserted, and during the truncation interval of the stream of OFDM symbols, the reset input is asserted during the intervals between symbols, as identified by the symbol timing identifier.A transmit filter for a stream of OFDM symbols, each symbol being separated into a first Tg interval, a second Tg interval, a symbol interval, and a final Tg interval, the filter has a stream modifier which discards the first Tg interval, accepts said second Tg interval, accepts the symbol interval and discards said final Tg interval, presenting to an infinite impulse response filter, in sequence, the second Tg interval, the symbol interval and the second Tg interval.

公开(公告)号：US20180308200A1

公开(公告)日：2018-10-25

申请号：US15494886

申请日：2017-04-24

申请人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06F17/16 ,  G06T1/60

CPC分类号： G06T1/20 ,  G06F8/41 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06F2009/45583 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/084

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type