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公开(公告)号：US20180308200A1
公开(公告)日：2018-10-25
申请号：US15494886
申请日：2017-04-24
申请人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC分类号： G06T1/20 , G06F8/41 , G06F9/45533 , G06F9/5061 , G06F9/5094 , G06F2009/45583 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/084
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a plurality of processing units each comprising a plurality of execution units (EUs), wherein the plurality of EUs comprise a first EU type and a second EU type
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公开(公告)号：US20180308206A1
公开(公告)日：2018-10-25
申请号：US15698217
申请日：2017-09-07
申请人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
发明人： Prasoonkumar Surti , Narayan Srinivasa , Feng Chen , Joydeep Ray , Ben J. Ashbaugh , Nicolas C. Galoppo Von Borries , Eriko Nurvitadhi , Balaji Vembu , Tsung-Han Lin , Kamal Sinha , Rajkishore Barik , Sara S. Baghsorkhi , Justin E. Gottschlich , Altug Koker , Nadathur Rajagopalan Satish , Farshad Akhbari , Dukhwan Kim , Wenyin Fu , Travis T. Schluessler , Josh B. Mastronarde , Linda L. Hurd , John H. Feit , Jeffery S. Boles , Adam T. Lake , Karthik Vaidyanathan , Devan Burke , Subramaniam Maiyuran , Abhishek R. Appu
CPC分类号： G06T1/20 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F3/1438 , G06N3/0445 , G06N3/0454 , G06N3/063 , G06N3/08 , G06N3/084 , G06T1/60 , G09G5/001 , G09G5/363 , G09G2352/00 , G09G2360/06 , G09G2360/08 , G09G2360/121 , G09G2360/123 , G09G2370/08
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.
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3.发明申请公开(公告)号：US20120254497A1
公开(公告)日：2012-10-04
申请号：US13074779
申请日：2011-03-29
申请人： YANG NI , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
发明人： YANG NI , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译： 一种促进异构平台中的共享指针的方法和装置。 在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的 处理核心。 异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。 通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。
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4.发明授权公开(公告)号：US08566537B2
公开(公告)日：2013-10-22
申请号：US13074779
申请日：2011-03-29
申请人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
发明人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译： 一种促进异构平台中的共享指针的方法和装置。 在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的 处理核心。 异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。 通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。
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5.发明申请公开(公告)号：US20140071144A1
公开(公告)日：2014-03-13
申请号：US14020616
申请日：2013-09-06
申请人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
发明人： Yang Ni , Rajkishore Barik , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Jayanth N. Rao , Ben J. Ashbaugh , Tomasz Janczak
IPC分类号： G06T1/60
CPC分类号： G06F12/0806 , G06F15/167 , G06T1/60
摘要： A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
摘要翻译： 一种促进异构平台中的共享指针的方法和装置。 在本发明的一个实施例中，异构或非均匀平台包括但不限于中央处理核心或单元，图形处理核心或单元，数字信号处理器，接口模块和任何其他形式的 处理核心。 异构平台具有促进共享指向CPU和GPU共享的存储器的位置的逻辑。 通过在异构平台中共享指针，可以简化异构平台中不同核心之间的数据或信息共享。
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公开(公告)号：US20060047662A1
公开(公告)日：2006-03-02
申请号：US10930597
申请日：2004-08-31
申请人： Rajkishore Barik , Manish Kurhedar
发明人： Rajkishore Barik , Manish Kurhedar
IPC分类号： G06F17/30
CPC分类号： G06F21/6227 , G06F2221/2141
摘要： A resource locator (such as a URL or similar reference) incorporates encrypted control information that is structured according to a predetermined format suited to a particular application. The control information is determined from the resource locator, and the resource locator is then processed in accordance with the control information. A response to a requested resource locator is returned.
摘要翻译： 资源定位符（例如URL或类似的引用）包含根据适合特定应用的预定格式而构造的加密控制信息。 从资源定位器确定控制信息，然后根据控制信息对资源定位器进行处理。 返回对所请求的资源定位器的响应。
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公开(公告)号：US20150220340A1
公开(公告)日：2015-08-06
申请号：US14129918
申请日：2013-10-04
CPC分类号： G06F9/30145 , G06F1/263 , G06F8/451 , G06F9/3822 , G06F9/5094 , G06F2209/508 , Y02D10/22
摘要： Various embodiments are generally directed to techniques for assigning instances of blocks of instructions of a routine to one of multiple types of core of a heterogeneous set of cores of a processor component. An apparatus to select types of cores includes a processor component; a core selection component for execution by the processor component to select a core of multiple cores to execute an initial subset of multiple instances of an instruction block in parallel based on characteristics of instructions of the instruction block, and to select a core of the multiple cores to execute remaining instances of the multiple instances of the instruction block in parallel based on characteristics of execution of the initial subset stored in an execution database; and a monitoring component for execution by the processor component to record the characteristics of execution of the initial subset in the execution database. Other embodiments are described and claimed.
摘要翻译： 各种实施例通常涉及用于将例程的指令块的实例分配给处理器组件的异构集群核心的多种类型的核心之一的技术。 选择核心类型的装置包括处理器组件; 核心选择部件，用于由处理器部件执行以选择多个核的核心，以基于指令块的指令的特性并行地执行指令块的多个实例的初始子集，并且选择多个核心的核心 基于存储在执行数据库中的初始子集的执行特性来并行执行指令块的多个实例的剩余实例; 以及用于由处理器组件执行以在执行数据库中记录初始子集的执行特性的监视组件。 描述和要求保护其他实施例。
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公开(公告)号：US07254809B2
公开(公告)日：2007-08-07
申请号：US10630023
申请日：2003-07-30
申请人： Manish Kurhekar , Pradeep Varma , Rajkishore Barik
发明人： Manish Kurhekar , Pradeep Varma , Rajkishore Barik
摘要： Methods, compiler apparatus and a computer program product for compiling UPC source code are disclosed. UPC-unique constructs are converted into C-level form. The C-level constructs are inserted into the source code to form a combined code. The combined code is translated into an intermediate form, wherein any surviving UPC-unique components are discarded. All UPC-unique data or statements are converted to a form that can be handled by general compiler architectures, yet retain UPC properties. The resultant intermediate form is converted to compiled machine code. The generation of C-level constructs occurs at a compiler front end module, avoiding difficulties in intermediate code handling.
摘要翻译： 公开了用于编译UPC源代码的方法，编译装置和计算机程序产品。 UPC唯一的构造转换为C级形式。 将C级结构插入到源代码中以形成组合代码。 组合的代码被转换成中间形式，其中任何幸存的UPC唯一组件被丢弃。 所有UPC唯一的数据或语句都将转换为可由一般编译器体系结构处理的表单，但保留UPC属性。 所得到的中间格式转换为编译的机器代码。 C级结构的生成发生在编译器前端模块，避免了中间代码处理的困难。
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9.发明授权公开(公告)号：US08732680B2
公开(公告)日：2014-05-20
申请号：US12388884
申请日：2009-02-19
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： Techniques for representing a program are provided. The techniques include creating one or more sub-variables for each of one or more variables in the program, and maintaining a single size of each of the one or more variables throughout a life-span of each of the one or more variables. Additionally, techniques for performing register allocation are also provided. The techniques include representing bit-width information of each of one or more variables in a powers-of-two representation, wherein the one or more variables comprise one or more variables in a program, coalescing the one or more variables, packing the one or more coalesced variables, and using the one or more packed variables to perform register allocation.
摘要翻译： 提供了代表程序的技术。 这些技术包括为程序中的一个或多个变量中的每个变量创建一个或多个子变量，并且在该一个或多个变量中的每一个的整个寿命期间维持一个或多个变量中的每一个的单个大小。 此外，还提供了用于执行寄存器分配的技术。 这些技术包括以二代表示方式表示一个或多个变量中的每一个的位宽信息，其中一个或多个变量包括程序中的一个或多个变量，合并一个或多个变量，打包一个或多个变量 更多的合并变量，并使用一个或多个压缩变量执行寄存器分配。
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公开(公告)号：US20100211937A1
公开(公告)日：2010-08-19
申请号：US12388884
申请日：2009-02-19
IPC分类号： G06F9/45
CPC分类号： G06F8/441
摘要： Techniques for representing a program are provided. The techniques include creating one or more sub-variables for each of one or more variables in the program, and maintaining a single size of each of the one or more variables throughout a life-span of each of the one or more variables. Additionally, techniques for performing register allocation are also provided. The techniques include representing bit-width information of each of one or more variables in a powers-of-two representation, wherein the one or more variables comprise one or more variables in a program, coalescing the one or more variables, packing the one or more coalesced variables, and using the one or more packed variables to perform register allocation.
摘要翻译： 提供了代表程序的技术。 这些技术包括为程序中的一个或多个变量中的每个变量创建一个或多个子变量，并且在该一个或多个变量中的每一个的整个寿命期间维持一个或多个变量中的每一个的单个大小。 此外，还提供了用于执行寄存器分配的技术。 这些技术包括以二代表示方式表示一个或多个变量中的每一个的位宽信息，其中一个或多个变量包括程序中的一个或多个变量，合并一个或多个变量，打包一个或多个变量 更多的合并变量，并使用一个或多个压缩变量执行寄存器分配。
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