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    PARALLEL OPERATION ON B+ TREES
    4.
    发明申请
    PARALLEL OPERATION ON B+ TREES 有权
    平行操作在B + TREES

    公开(公告)号：US20130339395A1

    公开(公告)日：2013-12-19

    申请号：US13996508

    申请日：2011-08-29

    申请人： Jason D. Sewall ,  Changkyu Kim ,  Jatin Chhugani ,  Nadathur Rajagopalan Satish

    发明人： Jason D. Sewall ,  Changkyu Kim ,  Jatin Chhugani ,  Nadathur Rajagopalan Satish

    IPC分类号： G06F17/30

    CPC分类号： G06F17/30327 ,  G06F9/5005 ,  G06F2209/5018

    摘要： Embodiments of techniques and systems for parallel processing of B+ trees are described. A parallel B+ tree processing module with partitioning and redistribution may include a set of threads executing a batch of B+ tree operations on a B+ tree in parallel. The batch of operations may be partitioned amongst the threads. Next, a search may be performed to determine which leaf nodes in the B+ tree are to be affected by which operations. Then, the threads may redistribute operations between each other such that multiple threads will not operate on the same leaf node. The threads may then perform B+ tree operations on the leaf nodes of the B+ tree in parallel. Subsequent modifications to nodes in the B+ may similarly be redistributed and performed in parallel as the threads work up the tree.

    摘要翻译： 描述了用于B +树的并行处理的技术和系统的实施例。 具有分区和再分配的并行B +树处理模块可以包括一组在B +树上并行执行一批B +树操作的线程。 该批操作可以在线程之间划分。 接下来，可以执行搜索以确定B +树中的哪些叶节点将受哪些操作影响。 然后，线程可以在彼此之间重新分配操作，使得多个线程将不在同一叶节点上操作。 然后，线程可以并行地在B +树的叶节点上执行B +树操作。 当线程处理树时，对B +中的节点的后续修改可以类似地重新分布并且并行执行。

    METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS
    5.
    发明申请
    METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS 有权
    流缓冲器管理指令的方法和装置

    公开(公告)号：US20120137074A1

    公开(公告)日：2012-05-31

    申请号：US12955763

    申请日：2010-11-29

    申请人： Daehyun Kim ,  Changkyu Kim ,  Victor W. Lee ,  Jatin Chhugani ,  Nadathur Rajagopalan Satish

    发明人： Daehyun Kim ,  Changkyu Kim ,  Victor W. Lee ,  Jatin Chhugani ,  Nadathur Rajagopalan Satish

    IPC分类号： G06F12/08 ,  G06F12/02 ,  G06F12/16

    CPC分类号： G06F12/0862 ,  G06F9/3004 ,  G06F2212/6022

    摘要： A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy.

    摘要翻译： 一种在处理器中执行流缓冲器管理指令的方法和系统。 在本发明的一个实施例中，流缓冲器管理指令有助于创建和使用处理器的专用存储空间或流缓冲器。 专用存储器空间是连续存储器空间，并且在本发明的一个实施例中具有顺序或线性寻址方案。 处理器具有执行流缓冲器管理指令的逻辑，以将来自源存储器地址的数据复制到用期望的存储器层级指定的目的地存储器地址。

    Cache and/or socket sensitive multi-processor cores breadth-first traversal
    6.
    发明授权
    Cache and/or socket sensitive multi-processor cores breadth-first traversal 有权
    缓存和/或套接字敏感的多处理器核宽度优先遍历

    公开(公告)号：US08533432B2

    公开(公告)日：2013-09-10

    申请号：US13629087

    申请日：2012-09-27

    申请人： Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhugani ,  Jason D. Sewall

    发明人： Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhugani ,  Jason D. Sewall

    IPC分类号： G06F9/38 ,  G06F9/06 ,  G06F15/80 ,  G06F13/14

    CPC分类号： G06F9/52

    摘要： Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are described. A vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. Potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. The threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed.

    摘要翻译： 描述了通过并行线程与缓存和/或套接字敏感的宽度优先遍历遍历图形的方法，装置和存储装置。 可以使用顶点访问阵列（VIS）来跟踪所访问的图形顶点。 VIS可以分为VIS子阵列，考虑到LLC的缓存大小，以减少驱逐的可能性。 可以使用潜在边界顶点阵列（PBV）来存储用于下一次迭代的潜在边界顶点，用于在当前迭代中被访问的顶点。 为每个线程生成的PBV的数量可以考虑多个套接字，所采用的处理器核在其上分布。 螺纹可以是负载平衡的; 可以考虑进一步的数据局部性意识以减少套接字间通信，和/或可以采用锁定和无原子的更新操作。

    CACHE AND/OR SOCKET SENSITIVE MULTI-PROCESSOR CORES BREADTH-FIRST TRAVERSAL
    7.
    发明申请
    CACHE AND/OR SOCKET SENSITIVE MULTI-PROCESSOR CORES BREADTH-FIRST TRAVERSAL 有权
    高速缓存和/或插座敏感多处理器最初的第一个TRAVERSAL

    公开(公告)号：US20130086354A1

    公开(公告)日：2013-04-04

    申请号：US13629087

    申请日：2012-09-27

    申请人： Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhuagani ,  Jason D. Sewall

    发明人： Nadathur Rajagopalan Satish ,  Changkyu Kim ,  Jatin Chhuagani ,  Jason D. Sewall

    IPC分类号： G06F15/80

    CPC分类号： G06F9/52

    摘要： Methods, apparatuses and storage device associated with cache and/or socket sensitive breadth-first iterative traversal of a graph by parallel threads, are disclosed. In embodiments, a vertices visited array (VIS) may be employed to track graph vertices visited. VIS may be partitioned into VIS sub-arrays, taking into consideration cache sizes of LLC, to reduce likelihood of evictions. In embodiments, potential boundary vertices arrays (PBV) may be employed to store potential boundary vertices for a next iteration, for vertices being visited in a current iteration. The number of PBV generated for each thread may take into consideration a number of sockets, over which the processor cores employed are distributed. In various embodiments, the threads may be load balanced; further data locality awareness to reduce inter-socket communication may be considered, and/or lock-and-atomic free update operations may be employed. Other embodiments may be disclosed or claimed.

    摘要翻译： 公开了通过并行线程与缓存和/或套接字敏感的宽度优先遍历遍历图形的方法，装置和存储装置。 在实施例中，可以采用顶点访问阵列（VIS）来跟踪所访问的图形顶点。 VIS可以分为VIS子阵列，考虑到LLC的缓存大小，以减少驱逐的可能性。 在实施例中，可以采用潜在边界顶点阵列（PBV）来存储针对当前迭代中被访问的顶点的下一次迭代的潜在边界顶点。 为每个线程生成的PBV的数量可以考虑多个套接字，所采用的处理器核在其上分布。 在各种实施例中，螺纹可以是负载平衡的; 可以考虑进一步的数据局部性意识以减少套接字间通信，和/或可以采用锁定和无原子的更新操作。 可以公开或要求保护其他实施例。