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    Phase calibration of clock signals
    22.
    发明授权
    Phase calibration of clock signals 有权

    公开(公告)号：US10129015B2

    公开(公告)日：2018-11-13

    申请号：US15659394

    申请日：2017-07-25

    Applicant: Rambus Inc.

    Inventor： Marko Aleksić ,  Simon Li ,  Roxanne Vu

    IPC: H04L7/033 ,  H04L7/00 ,  H04L25/03 ,  H03L7/081

    Abstract: A receiver with clock phase calibration. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.

    Synchronous wired-or ACK status for memory with variable write latency
    25.
    发明授权
    Synchronous wired-or ACK status for memory with variable write latency 有权
    具有可变写延迟的存储器的同步有线或ACK状态

    公开(公告)号：US09515204B2

    公开(公告)日：2016-12-06

    申请号：US13804334

    申请日：2013-03-14

    Applicant: Rambus Inc.

    Inventor： Yohan Frans ,  Simon Li ,  Eric Lindstadt ,  Jun Kim

    IPC: G06F12/02 ,  H01L31/0236 ,  G06F12/00 ,  G06F13/16

    CPC classification number: H01L31/02366 ,  G06F3/0613 ,  G06F3/0626 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/16 ,  G06F13/1684 ,  G06F13/372 ,  Y02D10/14

    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

    Abstract translation: 存储器控制器包括用于将存储器命令发送到与存储器控制器相关联的多个存储器件的命令接口。 存储器控制器还包括确认界面，用于通过耦合在存储器控制器和多个存储器件之间的共享确认链路从多个存储器设备接收确认状态分组，该确认状态分组指示该命令是否被多个 的存储器件。 此外，存储器控制器包括存储器控制器核心，用于对确认状态分组进行解码，以识别对应于多个存储器设备中的每一个的确认状态分组的一部分。

    Interface with Variable Data Rate
    26.
    发明申请
    Interface with Variable Data Rate 有权
    可变数据速率接口

    公开(公告)号：US20150092869A1

    公开(公告)日：2015-04-02

    申请号：US14507743

    申请日：2014-10-06

    Applicant: Rambus Inc.

    Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

    IPC: H04L1/00 ,  H04L25/02

    CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D50/10

    Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.

    Abstract translation: 一种设备包括耦合到节点的发射器，其中节点将耦合到有线链路。 发射机具有多种操作模式，包括校准模式，其中根据有线链路以预定错误率对应的电压裕度来确定有线链路上的通信数据速率的范围。 通信数据速率的范围包括最大数据速率，其可以是初始数据速率的非整数倍。

    SYNCHRONOUS WIRED-OR ACK STATUS FOR MEMORY WITH VARIABLE WRITE LATENCY
    29.
    发明申请
    SYNCHRONOUS WIRED-OR ACK STATUS FOR MEMORY WITH VARIABLE WRITE LATENCY 有权

    公开(公告)号：US20220077327A1

    公开(公告)日：2022-03-10

    申请号：US17445371

    申请日：2021-08-18

    Applicant: Rambus Inc.

    Inventor： Yohan Frans ,  Simon Li ,  John Eric Linstadt ,  Jun Kim

    IPC: H01L31/0236 ,  G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G06F13/372

    Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

    Serial link receiver with improved bandwidth and accurate eye monitor
    30.
    发明授权
    Serial link receiver with improved bandwidth and accurate eye monitor 有权

    公开(公告)号：US11184198B2

    公开(公告)日：2021-11-23

    申请号：US16811353

    申请日：2020-03-06

    Applicant: Rambus Inc.

    Inventor： Marko Aleksic ,  Pravin Kumar Venkatesan ,  Simon Li ,  Nikhil Vaidya

    IPC: H04L25/03 ,  H03M13/21 ,  H03M13/00 ,  H04L1/00

    Abstract: A receiver includes a decision circuit, a circuit to adjust an input signal of the decision circuit, a correction circuit and a control circuit. The decision circuit makes a data decision based on an input signal of the decision circuit. The circuit to adjust the input signal of the decision circuit adjusts the input signal of the decision circuit based on an input correction signal. The correction circuit combines a plurality of signals corresponding to different input correction parameters into a preliminary input correction signal. An input of the correction circuit is coupled to an output of the decision circuit. The control circuit maps the preliminary input correction signal into the input correction signal using a nonlinear code mapping.

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