公开(公告)号：US10008561B2

公开(公告)日：2018-06-26

申请号：US14977355

申请日：2015-12-21

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori Kaya ,  Yasushi Nakahara ,  Ryo Kanda ,  Tetsu Toda

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L27/02 ,  H03K19/0175 ,  H01L27/092 ,  H01L29/423

CPC classification number: H01L29/0619 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/402 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835 ,  H03K19/017509

Abstract: A semiconductor device including a first circuit region in which a first circuit whose power supply potential is a first voltage is formed; a second circuit region in which a second circuit whose power supply potential is a second voltage lower than the first voltage is formed a separation region which separates the first circuit region from the second circuit region; and a transistor which is located in the separation region and couples the second circuit to the first circuit and whose source and drain are of a first conductivity type, the separation region including an element separation film; a first field plate which overlaps with the element separation film in plan view; a plurality of conductive films which are provided over the first field plate.

公开(公告)号：US09906165B2

公开(公告)日：2018-02-27

申请号：US15194624

申请日：2016-06-28

Applicant: Renesas Electronics Corporation

Inventor： Kuniharu Muto ,  Koji Bando ,  Takamitsu Kanazawa ,  Ryo Kanda ,  Akihiro Tamura ,  Hirobumi Minegishi

IPC: H01L23/495 ,  H01L23/04 ,  H01L27/06 ,  H02M7/00 ,  H02M7/537 ,  H02M7/5387

CPC classification number: H02M7/537 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/49541 ,  H01L27/0664 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/181 ,  H02M7/003 ,  H02M7/53875 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

公开(公告)号：US09559687B2

公开(公告)日：2017-01-31

申请号：US14832867

申请日：2015-08-21

Applicant: Renesas Electronics Corporation

Inventor： Ryo Kanda ,  Tetsu Toda ,  Junichi Nakamura ,  Kazuyuki Umezu ,  Tomonobu Kurihara ,  Takahiro Nagatsu ,  Yasushi Nakahara ,  Yoshinori Kaya

IPC: H02P27/04 ,  H03K17/687 ,  H03K19/0185 ,  H03K5/24 ,  H03K17/567 ,  H02P27/06

CPC classification number: H03K3/356182 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7823 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H02P27/06 ,  H03K5/24 ,  H03K17/567 ,  H03K17/6872 ,  H03K19/018521

Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.

Abstract translation: 为了降低包括诸如驱动器IC的半导体器件的电力控制装置以及电子系统的成本等，驱动器IC包括高侧驱动器，电平移位电路，第一和第二晶体管， 和比较器电路。 第一晶体管形成在终端区域中。 第二晶体管形成在终端区域中并由第一电源电压驱动。 当感测节点的电压低于第一电源电压时，比较器电路形成在第一区域中以驱动第一晶体管导通，同时当感测节点的电压更高时驱动第一晶体管截止 比第一个电源电压。 第二晶体管是凹陷型晶体管。