公开(公告)号：US10068849B2

公开(公告)日：2018-09-04

申请号：US15073574

申请日：2016-03-17

Applicant: Renesas Electronics Corporation

Inventor： Koujirou Matsui ,  Takehiko Sakamoto ,  Kazuyuki Umezu ,  Tomoaki Uno

IPC: H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L23/482 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06 ,  H03K17/687

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

公开(公告)号：US11114527B2

公开(公告)日：2021-09-07

申请号：US16815636

申请日：2020-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Koshimizu ,  Hideki Niwayama ,  Kazuyuki Umezu ,  Hiroki Soeda ,  Atsushi Tachigami ,  Takeshi Iijima

IPC: H01L29/06 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49

Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.

公开(公告)号：US10396029B2

公开(公告)日：2019-08-27

申请号：US16005022

申请日：2018-06-11

Applicant: Renesas Electronics Corporation

Inventor： Koujirou Matsui ,  Takehiko Sakamoto ,  Kazuyuki Umezu ,  Tomoaki Uno

IPC: H01L23/528 ,  H03K17/687 ,  H01L23/532 ,  H01L27/088 ,  H01L23/482 ,  H01L29/40 ,  H01L29/78 ,  H01L29/06

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

公开(公告)号：US09711637B2

公开(公告)日：2017-07-18

申请号：US14406991

申请日：2014-01-31

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US09559687B2

公开(公告)日：2017-01-31

申请号：US14832867

申请日：2015-08-21

Applicant: Renesas Electronics Corporation

Inventor： Ryo Kanda ,  Tetsu Toda ,  Junichi Nakamura ,  Kazuyuki Umezu ,  Tomonobu Kurihara ,  Takahiro Nagatsu ,  Yasushi Nakahara ,  Yoshinori Kaya

IPC: H02P27/04 ,  H03K17/687 ,  H03K19/0185 ,  H03K5/24 ,  H03K17/567 ,  H02P27/06

CPC classification number: H03K3/356182 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7823 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H02P27/06 ,  H03K5/24 ,  H03K17/567 ,  H03K17/6872 ,  H03K19/018521

Abstract: In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor.

Abstract translation: 为了降低包括诸如驱动器IC的半导体器件的电力控制装置以及电子系统的成本等，驱动器IC包括高侧驱动器，电平移位电路，第一和第二晶体管， 和比较器电路。 第一晶体管形成在终端区域中。 第二晶体管形成在终端区域中并由第一电源电压驱动。 当感测节点的电压低于第一电源电压时，比较器电路形成在第一区域中以驱动第一晶体管导通，同时当感测节点的电压更高时驱动第一晶体管截止 比第一个电源电压。 第二晶体管是凹陷型晶体管。

公开(公告)号：US10074744B2

公开(公告)日：2018-09-11

申请号：US15625771

申请日：2017-06-16

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L29/10 ,  H01L23/535

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L24/05 ,  H01L24/06 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/04026 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/29101 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/32225

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US09866207B2

公开(公告)日：2018-01-09

申请号：US15387270

申请日：2016-12-21

Applicant: Renesas Electronics Corporation

Inventor： Ryo Kanda ,  Tetsu Toda ,  Junichi Nakamura ,  Kazuyuki Umezu ,  Tomonobu Kurihara ,  Takahiro Nagatsu ,  Yasushi Nakahara ,  Yoshinori Kaya

IPC: H02P27/04 ,  H03K3/356 ,  H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H03K17/567

CPC classification number: H03K3/356182 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7823 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/4903 ,  H02P27/06 ,  H03K5/24 ,  H03K17/567 ,  H03K17/6872 ,  H03K19/018521

Abstract: A driver integrated circuit includes a bootstrap circuit (BSC) configured to output a boot power supply voltage (VB) based on a first power supply voltage, the boot power supply voltage being higher than the first power supply voltage; a level shift circuit (LSC) configured to output an output pulse signal based on an input pulse signal and the boot power supply voltage; a high side driving circuit (HSU) configured to output a high side driving voltage based on the boot power supply voltage and the output pulse signal, wherein the bootstrap circuit includes a sense metal oxide semiconductor (MOS) transistor and a boot MOS transistor, wherein the sense MOS transistor includes a depression-type transistor.

公开(公告)号：US20170288053A1

公开(公告)日：2017-10-05

申请号：US15625771

申请日：2017-06-16

Applicant: Renesas Electronics Corporation

Inventor： Hideo Numabe ,  Nobuyuki Shirai ,  Hirokazu Kato ,  Tomoaki Uno ,  Kazuyuki Umezu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/423 ,  H01L29/08 ,  H01L29/06 ,  H01L23/535 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/7813 ,  H01L23/535 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1033 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/4236 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/45144 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.

公开(公告)号：US09318434B2

公开(公告)日：2016-04-19

申请号：US14470745

申请日：2014-08-27

Applicant: Renesas Electronics Corporation

Inventor： Koujirou Matsui ,  Takehiko Sakamoto ,  Kazuyuki Umezu ,  Tomoaki Uno

IPC: H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L23/482

CPC classification number: H01L23/528 ,  H01L23/4824 ,  H01L23/53214 ,  H01L23/53228 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7835 ,  H01L2224/16225 ,  H01L2924/19105 ,  H03K17/687

Abstract: A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Abstract translation: 在半导体衬底的主表面上的LDMOSFET形成区域中形成多个并联连接以构成功率MISFET的单位MISFET元件。 控制电源MISFET的栅极电压的控制电路形成在半导体衬底的主表面上的驱动电路区域中。 在半导体衬底上形成具有由相同金属材料制成的多个布线层的布线结构。 形成在LDMOSFET形成区域中的多个单位MISFET元件的栅电极通过形成在由同一金属材料制成的多个布线层的全部中的栅极布线彼此电连接。