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公开(公告)号：US4245299A
公开(公告)日：1981-01-13
申请号：US867262
申请日：1978-01-05
CPC分类号： G06F13/378 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle. Logic is provided in the first unit to enable the first unit to accept less parts of data than originally requested in the multiple fetch request. This permits the first unit to make multiple fetch requests of other units on the bus without regard to whether the other units are capable of performing multiple fetch operations and eliminates the need for abnormal condition recovery logic in the second unit. Logic is also provided to permit the first unit to utilize each part of data as it is received by the first unit without requiring the first unit to wait for the last transfer cycle before using any of the received parts of data.
摘要翻译： 在包括诸如数据处理系统之类的多个单元连接的公共总线的系统中，在异步生成的总线传送周期期间，信息可以由最高优先级单元传送。 逻辑被提供用于使第一单元（例如中央处理器）能够在第一传送周期期间进行诸如存储器的第二单元的多次提取请求。 多次提取请求请求第二单元在多个其它传送周期期间将多个数据部分传送到第一单元，其中在每个进一步的传送周期中传送一部分数据。 在第二单元中提供逻辑以使第二单元能够向第一单元指示，除了在最后一个进一步的传送周期内，每个进一步的传送周期将跟随另一传送周期。 在第一单元中提供逻辑以使得第一单元能够接收比原来在多次提取请求中要求的更少的数据部分。 这允许第一单元在总线上进行其他单元的多个提取请求，而不考虑其他单元是否能够执行多次获取操作，并且不需要第二单元中的异常状态恢复逻辑。 还提供逻辑以允许第一单元利用第一单元接收的数据的每个部分，而不需要第一单元在使用任何接收的数据部分之前等待最后的传送周期。
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公开(公告)号：US5983012A
公开(公告)日：1999-11-09
申请号：US128456
申请日：1993-09-28
申请人： Richard S. Bianchi , Dennis R. Flynn , Marcia T. Fogelgren , Richard A. Lemay , Mary E. Tovell , William E. Woods
发明人： Richard S. Bianchi , Dennis R. Flynn , Marcia T. Fogelgren , Richard A. Lemay , Mary E. Tovell , William E. Woods
CPC分类号： G06F21/31 , G06F13/10 , G06F13/105 , G06F21/6281 , G06F9/45537 , G06F2221/2105
摘要： An emulator executes on a second data processing system as a second system user level process including a first system user level program, a first system executive program, and first system user and executive tasks. An emulator level is interposed between the second system user level process and a kernel level and contains pseudo device drivers. Each pseudo device driver corresponds to a first system input/output device. The kernel level includes kernel processes, each kernel process corresponding to a pseudo device driver. The second system hardware platform includes a plurality of second system input/output devices, wherein each second system input output device corresponds to a kernel process. Each combination of a pseudo device driver, a corresponding kernel process and a corresponding second system input/output device executes in a second system process and emulates the operations of a corresponding first system input/output task and the corresponding first system input/output device. The pseudo device drivers are constructed of a plurality of pseudo device queues, a return queue and a queue manager.
摘要翻译： 模拟器在第二数据处理系统上执行，作为包括第一系统用户级程序，第一系统执行程序以及第一系统用户和执行任务的第二系统用户级进程。 在第二系统用户级别进程和内核级别之间插入一个仿真器级别，并包含伪设备驱动程序。 每个伪设备驱动程序对应于第一系统输入/输出设备。 内核级别包括内核进程，每个内核进程对应一个伪设备驱动程序。 第二系统硬件平台包括多个第二系统输入/输出设备，其中每个第二系统输入输出设备对应于内核进程。 伪设备驱动器，相应的内核进程和对应的第二系统输入/输出设备的每个组合在第二系统进程中执行并且模拟对应的第一系统输入/输出任务和对应的第一系统输入/输出设备的操作。 伪设备驱动程序由多个伪设备队列，返回队列和队列管理器构成。
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23.发明授权
公开(公告)号：US5136500A
公开(公告)日：1992-08-04
申请号：US366225
申请日：1989-06-12
IPC分类号： G06F13/16 , G06F15/167
CPC分类号： G06F15/167 , G06F13/1663
摘要： A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated with each local memory to control connection of any one of the local processors to its associated local memory. A local processor can also be connected via a controller and an adapter circuit connected to the controller to a system bus to obtain access to circuits connected thereto. In addition, a system processor connected to the system bus may also be connected to any particular one of the local memories via its associated controller and adapter connected thereto to load data or programs into the local memory for use by the local processors, and to read out the results of previous processing done by the local processors.
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公开(公告)号：US4935737A
公开(公告)日：1990-06-19
申请号：US927632
申请日：1986-11-05
IPC分类号： G06F7/76
CPC分类号： G06F7/76
摘要： A data selection matrix is disclosed which uses a plurality of programmed array logic (PAL) units having input thereto portions of binary words from a plurality of sources, the PALs being responsive to control words also input thereto to jointly select one of said sources of binary words and to select the arrangement of the portions of the binary words being input thereto from the selected source of binary words.
摘要翻译： 公开了一种数据选择矩阵，其使用多个编程的阵列逻辑（PAL）单元，其具有从多个源输入二进制字的部分，PAL响应于也输入到其的控制字来共同选择所述二进制源之一 并且从所选择的二进制字源中选择从其输入的二进制字的部分的排列。
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公开(公告)号：US4775929A
公开(公告)日：1988-10-04
申请号：US917940
申请日：1986-10-14
CPC分类号： G06F13/4217
摘要： What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement. Some of the processor circuits have a control lead input that is energized by the clock signal output from the system clock so that they accept information from one bus to which their input is connected during a first polarity portion of a clock cycle and return either unprocessed or processed information to another bus during a second polarity portion of a clock cycle.
摘要翻译： 所公开的是用于计算机系统中的时间分配总线布置，其中其中不同的电路通过多个总线互连，并且操作使得可以从一个电路中读出要处理的信息，以某种方式在另一个电路中进行处理 并且处理的信息在计算机系统中的系统时钟的一个周期内被存储在相同或另一个电路中，并且不需要连接到总线的电路中的总线控制电路和总线接口。 一些电路的输入/输出仅连接到总线中的单个总线，而其他电路的输入连接到一个总线，其输出连接到不同的总线，而其他电路的输入或输出连接到 总线中的一个和其他输入/输出连接到总线布置外部的电路。 一些处理器电路具有由从系统时钟输出的时钟信号激励的控制引线输入，使得它们在时钟周期的第一极性部分期间接收来自其输入连接到的一个总线的信息，并返回未处理的或 在时钟周期的第二极性部分处理信息到另一个总线。
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26.发明授权
公开(公告)号：US4460959A
公开(公告)日：1984-07-17
申请号：US302904
申请日：1981-09-16
CPC分类号： G06F12/0859
摘要： A logic control system comprised of a cache memory system and a transfer control logic unit is disclosed for accommodating the flow of both procedural information and CPU (central processing unit) instructions from a central memory system on a common communication bus to a CPU. The CPU and the transfer control logic unit communicate by way of the cache memory system with the common communication bus. In response to a CPU request to the central memory system, procedural information and instructions are requested by the transfer control logic unit from the cache memory system and presented to the CPU in such a manner as to avoid interruptions in CPU activity caused by information transfer delays.
摘要翻译： 公开了一种由高速缓冲存储器系统和传送控制逻辑单元组成的逻辑控制系统，用于将来自中央存储器系统的程序信息和CPU（中央处理单元）指令的流程从公共通信总线上的CPU接收到CPU。 CPU和传输控制逻辑单元通过具有公共通信总线的高速缓冲存储器系统进行通信。 响应于对中央存储器系统的CPU请求，传输控制逻辑单元从高速缓冲存储器系统请求程序信息和指令，并以这样的方式呈现给CPU，以避免由信息传输延迟引起的CPU活动中断 。
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公开(公告)号：US4308589A
公开(公告)日：1981-12-29
申请号：US93096
申请日：1979-11-08
CPC分类号： G06F9/30014 , G06F9/30036
摘要： The performance of a scientific ADD instruction is improved by storing the mantissas of both operands in each of two random access memories, selecting the mantissa with the smaller exponent, shifting that mantissa and performing the ADD operation of adding the mantissas in one machine cycle.
摘要翻译： 通过将两个操作数的尾数存储在两个随机存取存储器中的每一个中，选择具有较小指数的尾数，移动该尾数并执行在一个机器周期中添加尾数的ADD操作来改进科学ADD指令的性能。
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公开(公告)号：US4047247A
公开(公告)日：1977-09-06
申请号：US674517
申请日：1976-04-07
CPC分类号： G06F9/355
摘要： A final effective address of an operand is generated in a microprogrammed data processing system by use of a base address register which may include an unindexed address, an index register which may include an index address value, an instruction register which may include an instruction word, which instruction word provides control over the addressing of a control store dependent upon the state of a selected one of a plurality of test conditions. The addressed control store word provides signals for controlling the operation of the system, including the branching between such major operations as instruction fetching, addressing, reading, writing, and execution as well as branching between minor operations which are included in the major operations.
摘要翻译： 操作数的最终有效地址在微程序数据处理系统中通过使用可包括无索引地址的基址寄存器，可包括索引地址值的索引寄存器，可包括指令字的指令寄存器， 该指令字取决于多个测试条件中所选择的一个的状态来提供对控制存储器的寻址的控制。 寻址的控制存储字提供用于控制系统操作的信号，包括在诸如指令获取，寻址，读取，写入和执行之类的主要操作之间的分支以及在主要操作中包括的次要操作之间的分支。
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公开(公告)号：US4363095A
公开(公告)日：1982-12-07
申请号：US221851
申请日：1980-12-31
申请人： William E. Woods , Arthur Peters
发明人： William E. Woods , Arthur Peters
CPC分类号： G06F12/0851
摘要： In a data processing system a cache memory comprises level one and level two even and odd data stores and level one and level two even and odd directory stores. The directory stores include a plurality of storage locations for storing the most significant bits of the address numbers associated with the data words stored in the level one and level two even and odd data stores. The level one and level two even and odd directory stores are addressed by the least significant bits of the address numbers. Comparator circuits compare the high order bits of an address number supplied in a memory request to the high order bits stored in the level one even and odd directory stores at storage locations identified by both the low order bits of the address supplied in the memory request and the low order address bits incremented by one. A hit detector circuit determines whether one, both, or none of the requested words are stored in the cache memory by analyzing the outputs of the comparators.
摘要翻译： 在数据处理系统中，高速缓冲存储器包括一级和二级偶数和奇数数据存储，以及一级和二级偶数和奇数目录存储。 目录存储包括用于存储与存储在一级和二级偶数和奇数数据存储中的数据字相关联的地址号的最高有效位的多个存储位置。 一级和二级偶数和奇数目录存储由地址号的最低有效位寻址。 比较器电路将存储器请求中提供的地址号码的高位比较与存储在一级偶数和奇数目录中的高位比特存储在由存储器请求中提供的地址的低位比特识别的存储位置处， 低位地址位递增1。 命中检测器电路通过分析比较器的输出来确定所请求的字中的一个，两个，还是没有一个被存储在高速缓冲存储器中。
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公开(公告)号：US4079451A
公开(公告)日：1978-03-14
申请号：US674698
申请日：1976-04-07
CPC分类号： G06F9/30018 , G06F12/04
摘要： A data processing system for providing word, byte or bit addressing. A word location in a memory device may be addressed based upon the contents of a base address register. Indirect addressing may be provided to another word location based upon a word index value in an index register. Effective byte or bit addressing of the addressed word is provided in response to byte and bit index values which are produced by means of the index register. An instruction word indicates the type of addressing and directs the use of different control words included in a control storage device in order to implement the desired operation.
摘要翻译： 一种用于提供字，字节或位寻址的数据处理系统。 可以基于基地址寄存器的内容来寻址存储器设备中的字位置。 可以基于索引寄存器中的单词索引值将间接寻址提供给另一单词位置。 响应于通过索引寄存器产生的字节和位索引值，提供寻址字的有效字节或位寻址。 指令字指示寻址的类型并指示使用包括在控制存储设备中的不同控制字，以便实现期望的操作。
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