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41 条记录 (耗时 0.026 秒)

    Semiconductor having thick dielectric regions
    21.
    发明申请
    Semiconductor having thick dielectric regions 失效
    半导体具有较厚的电介质区域

    公开(公告)号：US20060163690A1

    公开(公告)日：2006-07-27

    申请号：US11384565

    申请日：2006-03-20

    申请人： Richard Blanchard

    发明人： Richard Blanchard

    IPC分类号： H01L21/76 ,  H01L29/00

    CPC分类号： H01L29/66712 ,  H01L21/26586 ,  H01L21/76208 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/66333

    摘要： A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The method also includes providing in the semiconductor substrate one or more trenches, first mesas and second mesas. The method also includes oxidizing sidewalls and bottoms of each trench; depositing a doped oxide into each trench and on the tops of the first and second mesas; and thermally oxidizing the semiconductor substrate at a temperature sufficient enough to cause the deposited oxide to flow so that the silicon in each of the first mesas is completely converted to silicon dioxide while the silicon in each of the second mesas is only partially converted to silicon dioxide and so that each of the trenches is filled with oxide.

    摘要翻译： 一种制造半导体器件的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。 该方法还包括在半导体衬底中提供一个或多个沟槽，第一台面和第二台面。 该方法还包括氧化每个沟槽的侧壁和底部; 将掺杂的氧化物沉积到第一和第二台面的每个沟槽和顶部; 以及在足以使沉积的氧化物流动的温度下热氧化半导体衬底，使得每个第一台面中的硅完全转化为二氧化硅，而每个第二台面中的硅仅部分转化为二氧化硅 并且使得每个沟槽都填充有氧化物。

    High voltage power MOSFET having low on-resistance
    22.
    发明申请
    High voltage power MOSFET having low on-resistance 失效

    公开(公告)号：US20060125003A1

    公开(公告)日：2006-06-15

    申请号：US11342484

    申请日：2006-01-30

    申请人： Richard Blanchard

    发明人： Richard Blanchard

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7802 ,  H01L21/2255 ,  H01L21/2257 ,  H01L22/26 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.

    High voltage power MOSFET having a voltage sustaining region that includes Doped Columns Formed by trench etching and diffusion from regions of oppositely doped polysilicon
    24.
    发明申请
    High voltage power MOSFET having a voltage sustaining region that includes Doped Columns Formed by trench etching and diffusion from regions of oppositely doped polysilicon 有权
    具有电压维持区域的高压功率MOSFET，其包括通过沟槽蚀刻和相对掺杂多晶硅区域扩散形成的掺杂色谱柱

    公开(公告)号：US20050042830A1

    公开(公告)日：2005-02-24

    申请号：US10945018

    申请日：2004-09-20

    申请人： Richard Blanchard

    发明人： Richard Blanchard

    IPC分类号： H01L21/331 ,  H01L21/22 ,  H01L21/225 ,  H01L21/329 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/732 ,  H01L29/78

    CPC分类号： H01L29/7802 ,  H01L21/2257 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/1095 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395

    摘要： A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon. Finally, at least one region of the second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

    摘要翻译： 提供了形成功率半导体器件的方法。 该方法开始于提供第一或第二导电类型的衬底，然后在衬底上形成电压维持区域。 通过在衬底上沉积第一导电类型的外延层并在外延层中形成至少一个沟槽来形成电压维持区。 具有第二导电类型的第二掺杂剂的第一多晶硅层沉积在沟槽中。 第二掺杂剂被扩散以形成与沟槽和外延层相邻的掺杂外延区域。 随后将具有第一导电类型的第一掺杂剂的第二多晶硅层沉积在沟槽中。 分别位于第二和第一多晶硅层中的第一和第二掺杂剂是相互扩散的，以在多晶硅的第一和第二层中实现电补偿。 最后，在电压维持区域上形成第二导电类型的至少一个区域以限定它们之间的接合。

    Terminations for semiconductor devices with floating vertical series capacitive structures
    30.
    发明申请
    Terminations for semiconductor devices with floating vertical series capacitive structures 审中-公开
    具有浮动垂直串联电容结构的半导体器件的端接

    公开(公告)号：US20070012983A1

    公开(公告)日：2007-01-18

    申请号：US11487142

    申请日：2006-07-14

    申请人： Robert Yang ,  Richard Blanchard ,  Francois Hebert

    发明人： Robert Yang ,  Richard Blanchard ,  Francois Hebert

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7803 ,  H01L29/404 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

    摘要： This invention relates to achieving high breakdown voltage and low on-resistance in semiconductor devices that have top, intermediate and bottom regions with a controllable current path traversing any of these regions. The device has an insulating trench that is coextensive with the top and intermediate regions and girds these regions from at least one side and preferably from both or all sides. A series capacitive structure with a biased top element and a number of floating elements is disposed in the insulating trench, and the intermediate region is endowed with a capacitive property that is chosen to establish a capacitive interaction or coupling between the series capacitive structure and the intermediate region so that the breakdown voltage VBD is maximized and on-resistance is minimized. A second series capacitive structure disposed in a second insulating trench can be employed to terminate the device.

    摘要翻译： 本发明涉及在半导体器件中实现高击穿电压和低导通电阻，所述半导体器件具有穿过任何这些区域的可控电流路径的顶部区域，中间区域和底部区域。 该装置具有与顶部和中间区域共同延伸的绝缘沟槽，并且从至少一个侧面，优选地从两侧或全部侧面将这些区域线化。 具有偏置顶部元件和多个浮动元件的串联电容结构设置在绝缘沟槽中，并且中间区域具有被选择用于建立串联电容结构和中间体之间的电容性相互作用或耦合的电容性质 区域，使得击穿电压V BAT最大化，导通电阻最小化。 可以采用设置在第二绝缘沟槽中的第二串联电容结构来终止该器件。