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    Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
    22.
    发明授权
    Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution 失效
    在执行无序指令执行的处理器中，使用多周期凸轮准备选择依赖于数据的指令

    公开(公告)号：US5546597A

    公开(公告)日：1996-08-13

    申请号：US203050

    申请日：1994-02-28

    申请人： Robert W. Martell ,  Glenn J. Hinton ,  Michael A. Fetterman ,  David B. Papworth ,  Robert P. Colwell ,  Andrew F. Glew

    发明人： Robert W. Martell ,  Glenn J. Hinton ,  Michael A. Fetterman ,  David B. Papworth ,  Robert P. Colwell ,  Andrew F. Glew

    IPC分类号： G06F9/38 ,  G06F9/345

    CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

    摘要： An instruction dispatch circuit is disclosed that improves instruction execution throughput for a processor. The instruction dispatch circuit comprises an instruction buffer with a plurality of instruction entries and a content addressable memory array having at least one cam entry corresponding to each instruction entry. Each cam entry stores at least one source tag for the corresponding instruction entry. The content addressable memory array matches to a result tag from an execution circuit over a result bus, wherein the execution circuit transfers the result tag over the result bus at least one clock cycle before transferring a corresponding result data value over the result bus. Each cam entry generates a cam match signal used to determine whether data dependent instruction are ready for dispatch.

    摘要翻译： 公开了一种提高处理器的指令执行吞吐量的指令调度电路。 指令调度电路包括具有多个指令条目的指令缓冲器和具有对应于每个指令条目的至少一个凸轮条目的内容可寻址存储器阵列。 每个凸轮条目存储用于相应指令条目的至少一个源标签。 内容可寻址存储器阵列通过结果总线与来自执行电路的结果标签相匹配，其中执行电路在通过结果总线传送相应的结果数据值之前至少一个时钟周期在结果总线上传送结果标签。 每个凸轮条目产生一个凸轮匹配信号，用于确定数据相关指令是否准备好进行发送。

    Coordinating speculative and committed state register source data and immediate source data in a processor
    23.
    发明授权
    Coordinating speculative and committed state register source data and immediate source data in a processor 失效
    在处理器中协调推测和提交的状态寄存器源数据和即时源数据

    公开(公告)号：US5452426A

    公开(公告)日：1995-09-19

    申请号：US177240

    申请日：1994-01-04

    申请人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

    发明人： David B. Papworth ,  Glenn J. Hinton ,  Michael A. Fetterman ,  Robert P. Colwell ,  Andrew F. Glew

    IPC分类号： G06F9/38 ,  G06F9/24 ,  G06F9/28

    CPC分类号： G06F9/30167 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

    摘要： A mechanism for coordinating source data in a processor, wherein a decode circuit issues instructions comprising at least one immediate valid flag and at least one logical register source. The immediate valid flag indicates whether an immediate operand for the instruction is available on an immediate data bus, and the logical register source specifies a physical register or a committed state register. A speculative result data value and a speculative source valid flag are read from the physical register, and a committed result data value is read from the committed state register. The speculative result data value and the speculative source valid flag or the committed result data value and the committed source valid flag provide a source data value and a source data valid flag for scheduling an execution of the instruction.

    摘要翻译： 一种用于在处理器中协调源数据的机制，其中解码电路发出包括至少一个即时有效标志和至少一个逻辑寄存器源的指令。 即时有效标志指示在立即数据总线上是否有指令的立即操作数可用，逻辑寄存器源指定物理寄存器或提交状态寄存器。 从物理寄存器读取推测结果数据值和推测源有效标志，并从承诺状态寄存器读取提交结果数据值。 推测结果数据值和推测源有效标志或提交结果数据值和提交的源有效标志提供源数据值和源数据有效标志，用于调度指令的执行。

    Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor
    26.
    发明授权
    Method and apparatus for maximum throughput scheduling of dependent operations in a pipelined processor 失效
    用于流水线处理器中依赖操作的最大吞吐量调度的方法和装置

    公开(公告)号：US6101597A

    公开(公告)日：2000-08-08

    申请号：US176370

    申请日：1993-12-30

    申请人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

    发明人： Robert P. Colwell ,  Michael A. Fetterman ,  Glenn J. Hinton ,  Robert W. Martell ,  David B. Papworth

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3824 ,  G06F9/383

    摘要： Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM). Before an instruction is executed and its result data written back, the storage location address of the result is provided to the CAM and associatively compared with the source operand addresses stored therein. A CAM match and its accompanying match bit indicate that the result of the instruction to be executed will provide a source operand to the dependent instruction waiting in the reservation station. Using a bypass mechanism, if the operand is computed after dispatch of the dependent instruction, then the source operand is provided directly from the execution unit computing the source operand to a source operand input of the execution unit executing the dependent instruction.

    摘要翻译： 通过最大化处理器确定依赖指令的源操作数的可用性的效率，并将这些操作数提供给执行依赖的执行单元，从而实现流水线处理器中相关指令的最大吞吐量或“背对背” 指令。 这两个操作通过多个机制来实现。 用于确定源操作数的可用性以及因此用于发送到可用执行单元的依赖指令的准备的机制依赖于在操作数本身实际计算之前源操作数的可用性的预期确定 执行另一条指令。 指令的源操作数的存储地址存储在内容可寻址存储器（CAM）中。 在执行指令并且其结果数据被写回之前，将结果的存储位置地址提供给CAM并与存储在其中的源操作数地址相关联地进行比较。 CAM匹配及其伴随的匹配位指示要执行的指令的结果将为在保留站等待的从属指令提供源操作数。 使用旁路机制，如果在分派依赖指令之后计算操作数，则将操作数从执行单元直接提供到计算源操作数到执行依赖指令的执行单元的源操作数输入。

    Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system
    27.
    发明授权
    Methods and apparatus for determining the next instruction pointer in an out-of-order execution computer system 失效
    用于确定无序执行计算机系统中的下一个指令指针的方法和装置

    公开(公告)号：US5463745A

    公开(公告)日：1995-10-31

    申请号：US174074

    申请日：1993-12-22

    申请人： Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

    发明人： Rohit A. Vidwans ,  Darrell D. Boggs ,  Michael A. Fetterman ,  Andrew F. Glew

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3885 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

    摘要： Instructions are fetched and issued by an instruction fetch and issue circuit with the instructions' sizes in program order. An allocate circuit allocates reservation station entries in a reservation station circuit, and reorder buffer entries in a reorder circuit, for the issued instructions in order, storing the instructions' sizes in the allocated reorder buffer entries. The reservation and dispatch circuit dispatches the issued instructions to the execution circuits for execution when they are ready. The execution circuits store the result data including target addresses of branch instructions into the corresponding reorder buffer entries. During each retirement operation, a retire circuit reads the instruction sizes and the target addresses for a predetermined number of issued instructions from their allocated reorder buffer entries. The retire circuit determines two or more speculative next instruction pointers for each of the issued instructions, factoring into consideration whether the issued instructions are branch instructions or not, and their relative positions to each other. Each of the speculative next instruction pointers indicates what the next instruction pointer for the processor should be for retiring a particular combination of the result data values of the issued instructions under consideration. The retire circuit conditionally updates the next instruction pointer with one of the speculative next instruction pointers, depending on how many, if any, of the instructions can actually retire, and whether any of the actually retiring instructions are branch instructions.

    摘要翻译： 指令由指令提取和发布电路以指令的大小以程序顺序取出并发出。 分配电路在保留站电路中分配保留站条目，并且重新排序重新排序电路中的缓冲区条目，以便按顺序发布指令，将指令的大小存储在所分配的重排序缓冲器条目中。 预约和调度电路在准备就绪时将发出的指令发送到执行电路执行。 执行电路将包括分支指令的目标地址的结果数据存储到相应的重排序缓冲器条目中。 在每个退休操作期间，退出电路从其分配的重排序缓冲器条目读取预定数量的已发布指令的指令大小和目标地址。 退出电路为每个发出的指令确定两个或更多个推测下一个指令指针，考虑所发出的指令是否是分支指令，以及它们彼此的相对位置。 每个推测下一个指令指针指示处理器的下一个指令指针应该用于退出所考虑的已发出指令的结果数据值的特定组合。 退出电路有条件地使用推测下一个指令指针之一更新下一个指令指针，这取决于指令实际可以退出多少（如果有的话），以及是否有任何实际退出的指令是分支指令。

    Apparatus and method for handling string operations in a pipelined processor
    28.
    发明授权
    Apparatus and method for handling string operations in a pipelined processor 失效
    在流水线处理器中处理字符串操作的装置和方法

    公开(公告)号：US5404473A

    公开(公告)日：1995-04-04

    申请号：US204612

    申请日：1994-03-01

    申请人： David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Lawrence O. Smith, III ,  Michael M. Hancock ,  Beth Schultz

    发明人： David B. Papworth ,  Michael A. Fetterman ,  Andrew F. Glew ,  Lawrence O. Smith, III ,  Michael M. Hancock ,  Beth Schultz

    IPC分类号： G06F9/308 ,  G06F9/32 ,  G06F9/38 ,  G06F13/00

    CPC分类号： G06F9/30018 ,  G06F9/325 ,  G06F9/3842

    摘要： In a pipelined processor, an apparatus for handling string operations. When a string operation is received by the processor, the length of the string as specified by the programmer is stored in a register. Next, an instruction sequencer issues an instruction that computes the register value minus a pre-determined number of iterations to be issued into the pipeline. Following the instruction, the pre-determined number of iterations are issued to the pipeline. When the instruction returns with the calculated number, the instruction sequencer then knows exactly how many iterations should be executed. Any extra iterations that had initially been issued are canceled by the execution unit, and additional iterations are issued as necessary. A loop counter in the instruction sequencer is used to track the number of iterations.

    摘要翻译： 在流水线处理器中，用于处理字符串操作的装置。 当处理器接收到字符串操作时，由编程器指定的字符串的长度存储在寄存器中。 接下来，指令定序器发出计算寄存器值减去要发布到流水线中的预定数量的迭代的指令。 按照该指令，将预先确定的迭代次数发布到流水线。 当指令以计算出的数字返回时，指令定序器将准确地知道应该执行多少次迭代。 最初发布的任何额外的迭代将被执行单元取消，并根据需要发出额外的迭代。 指令定序器中的循环计数器用于跟踪迭代次数。

    Segment register renaming in an out of order processor
    29.
    发明授权
    Segment register renaming in an out of order processor 失效
    分段寄存器在乱序处理器中重命名

    公开(公告)号：US5951670A

    公开(公告)日：1999-09-14

    申请号：US923496

    申请日：1997-09-04

    申请人： Andrew F. Glew ,  Michael A. Fetterman

    发明人： Andrew F. Glew ,  Michael A. Fetterman

    IPC分类号： G06F9/30 ,  G06F15/00

    CPC分类号： G06F9/30098 ,  G06F9/3013 ,  G06F9/384

    摘要： A processor for executing a plurality of instructions. The processor comprises a plurality of logical segment registers, wherein the logical segment registers define an architectural state for memory segmentation of the processor. A plurality of physical segment registers are coupled to the logical segment registers. The processor further comprises an issue cluster that issues the instructions and that maps the logical segment registers, specified by the operations, to the physical segment registers to provide segment register renaming in the processor.

    摘要翻译： 一种用于执行多个指令的处理器。 处理器包括多个逻辑段寄存器，其中逻辑段寄存器定义用于处理器的存储器分段的架构状态。 多个物理段寄存器耦合到逻辑段寄存器。 该处理器还包括发出指令并将由操作指定的逻辑段寄存器映射到物理段寄存器的问题簇，以在处理器中提供段寄存器重命名。