公开(公告)号：US12167601B2

公开(公告)日：2024-12-10

申请号：US18188946

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Geunwon Lim ,  Manjoong Kim

IPC: H10B41/10 ,  H10B41/27 ,  H10B41/30 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35

Abstract: A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

公开(公告)号：US12137555B2

公开(公告)日：2024-11-05

申请号：US18348521

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US12002511B2

公开(公告)日：2024-06-04

申请号：US17353918

申请日：2021-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Jinwoo Park ,  Ilgyu Choi

IPC: H10B41/10 ,  G11C16/04 ,  H10B41/20 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0483 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: Semiconductor devices may include a peripheral circuit structure including circuits, a substrate on the peripheral circuit structure, a pair of word line cut structures extending in a first direction on the substrate, and a memory cell block between the pair of word line cut structures and on the substrate. The memory cell block may include a memory stack structure including gate lines overlapping each other in a vertical direction, an interlayer insulation layer on an edge portion of each of the gate lines, a dam structure extending through the gate lines and the interlayer insulation layer, an intersection direction cut structure extending through the memory stack structure and the interlayer insulation layer in the vertical direction and being spaced apart from the dam structure, and a dummy channel structures between the intersection direction cut structure and the dam structure.

公开(公告)号：US11985820B2

公开(公告)日：2024-05-14

申请号：US17348172

申请日：2021-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kangmin Kim ,  Jaehoon Shin ,  Dongseog Eun ,  Geunwon Lim

IPC: H10B41/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/40 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a first substrate; devices on the first substrate; a second substrate on the devices; gate electrodes stacked on the second substrate and spaced apart from each other in a first direction; channel structures penetrating the gate electrodes, extending in the first direction, and including a channel layer; isolation regions penetrating the gate electrodes and extending in a second direction; a through contact plug penetrating the second substrate, extending in the first direction, and electrically connecting the gate electrodes to the devices; a barrier structure spaced apart from the through contact plug and surrounding the through contact plug; and a support structure on the gate electrodes and including support patterns, wherein the support structure has first through regions spaced apart from each other in the second direction on the isolation regions and a second through region in contact with an upper surface of the barrier structure.

公开(公告)号：US11744066B2

公开(公告)日：2023-08-29

申请号：US17685692

申请日：2022-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwon Lim ,  Seokcheon Baek

IPC: H10B41/27 ,  G11C5/02 ,  H01L29/788

CPC classification number: H10B41/27 ,  G11C5/025 ,  H01L29/788

Abstract: A semiconductor device includes a lower structure and a stack structure that extends into a connection region on the lower structure, where the stack structure includes gate pads and mold pads. The mold pads include intermediate mold pads that include first intermediate mold pads and a second intermediate mold pad between a pair of the first intermediate mold pads, each of the first intermediate mold pads has a first length in a first direction, the second intermediate mold pad has a second length in the first direction, greater than the first length, one of the intermediate mold pads includes a mold pad portion and an insulating protrusion portion on the mold pad portion, one of the first intermediate mold pads includes the mold pad portion and the insulating protrusion portion, and a central region of the second intermediate mold pad does not include the insulating protrusion portion.

公开(公告)号：US11362105B2

公开(公告)日：2022-06-14

申请号：US16902489

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin Song ,  Kangmin Kim ,  Joongshik Shin ,  Geunwon Lim

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/1157

Abstract: A vertical memory device includes gate electrode structures, channels, first to third division patterns, and a first support layer. The gate electrode structure includes gate electrodes stacked in a first direction, and extends in a second direction. The gate electrode structures are spaced apart from one another in a third direction. The first division pattern extends in the second direction between the gate electrode structures. The second and third division patterns are alternately disposed in the second direction between the gate electrode structures. The first support layer is on the gate electrode structures at substantially the same height as upper portions of the first and second division patterns, and contacts the upper portions of the first and second division patterns. The upper portions of the first and second division patterns are arranged in a zigzag pattern in the second direction in a plan view.

公开(公告)号：US11069698B2

公开(公告)日：2021-07-20

申请号：US16398442

申请日：2019-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyoung Kim ,  Kwang-Soo Kim ,  Geunwon Lim ,  Jisung Cheon

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/311

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

公开(公告)号：US10964714B2

公开(公告)日：2021-03-30

申请号：US16259086

申请日：2019-01-28

Applicant: Samsung Electronics Co., Ltd

Inventor： Geunwon Lim ,  SangJun Hong ,  Seokcheon Baek

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11556

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including gate electrodes sequentially stacked on the substrate, a source structure between the electrode structure and the substrate, vertical semiconductor patterns passing through the electrode structure and the source structure, a data storage pattern between each of the vertical semiconductor patterns and the electrode structure, and a common source pattern between the source structure and the substrate. The common source pattern has a lower resistivity than the source structure and is connected to the vertical semiconductor patterns through the source structure.

公开(公告)号：US10665606B2

公开(公告)日：2020-05-26

申请号：US16222059

申请日：2018-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokcheon Baek ,  Geunwon Lim ,  Hwan Lee

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/66 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/105

Abstract: A three-dimensional semiconductor memory device includes a horizontal semiconductor layer on a peripheral logic structure, a cell electrode structure including cell gate electrodes vertically stacked on the horizontal semiconductor layer, ground selection gate electrodes provided between the cell electrode structure and the horizontal semiconductor layer and horizontally spaced apart from each other, each of the ground selection gate electrodes including first and second pads spaced apart from each other with the cell electrode structure interposed therebetween in a plan view, a first through-interconnection structure connecting the first pads of the ground selection gate electrodes to the peripheral logic structure, and a second through-interconnection structure connecting the second pads of the ground selection gate electrodes to the peripheral logic structure.