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    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20250062286A1

    公开(公告)日：2025-02-20

    申请号：US18588462

    申请日：2024-02-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyunsoo Chung ,  Kwang-Soo Kim ,  Jun Gul Hwang

    IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H10B80/00

    Abstract: A semiconductor package includes a first semiconductor chip having a front side and a back side that is opposite to the front side, the first semiconductor chip includes a front side wiring structure disposed on the front side, a back side wiring structure disposed on the back side, and a first through via electrically connected to the front side wiring structure and the back side wiring structure, a second semiconductor chip disposed on the back side of the first semiconductor chip and including a second through via, and a third semiconductor chip disposed on the front side of the first semiconductor chip, wherein the first semiconductor chip receives power through the second through via, and wherein a thickness of the second semiconductor chip is greater than a thickness of the first semiconductor chip.

    Semiconductor memory devices including protrusion pads
    2.
    发明授权
    Semiconductor memory devices including protrusion pads 有权

    公开(公告)号：US10229929B2

    公开(公告)日：2019-03-12

    申请号：US15652648

    申请日：2017-07-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwang-Soo Kim ,  Se Mee Jang

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/1157 ,  H01L23/535

    Abstract: Disclosed is a semiconductor memory device may include a substrate including a cell array region and a contact region and a stacking structure including a plurality of insulating layers and a plurality of gate electrodes alternately stacked on the substrate. The stacking structure may include a stepwise structure in the contact region. Ones of the plurality of gate electrodes may include a respective pad unit that comprises a step of the stepwise structure. At least one of the pad units may include a base pad and a protrusion pad on the base pad. The protrusion pad may be between and spaced apart from two edges of a surface of the base pad that are perpendicular to an extension direction of the respective gate electrode.

    Vertical memory device including common source line structure
    4.
    发明授权
    Vertical memory device including common source line structure 有权

    公开(公告)号：US10535599B2

    公开(公告)日：2020-01-14

    申请号：US15831498

    申请日：2017-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-Soo Kim

    IPC: H01L23/522 ,  H01L23/528 ,  H01L27/115 ,  H01L27/11582 ,  H01L49/02

    Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME, AND ELECTRONIC SYSTEM INCLUDING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250133742A1

    公开(公告)日：2025-04-24

    申请号：US18783638

    申请日：2024-07-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Suseong Noh ,  Ilho Myeong ,  Kwang-Soo Kim

    IPC: H10B51/20 ,  H10B51/30

    Abstract: A semiconductor device includes: a substrate, a gate stacking structure that includes a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on the substrate, a channel layer that extends in a first direction and into the gate stacking structure, where the channel layer is electrically connected to the substrate, a channel insulating layer that at least partially surrounds the channel layer, and a plurality of dielectric layers that are between the channel insulating layer and the plurality of gate electrodes, extend along a circumference of the channel layer, and are spaced apart from each other in the first direction, where each of the plurality of dielectric layers includes: a ferroelectric pattern that at least partially surrounds the channel insulating layer, and an anti-ferroelectric pattern that at least partially surrounds the ferroelectric pattern.

    Imaging apparatus and imaging method
    7.
    发明授权
    Imaging apparatus and imaging method 有权

    公开(公告)号：US10429315B2

    公开(公告)日：2019-10-01

    申请号：US16037088

    申请日：2018-07-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Akio Ishikawa ,  Ken Ozawa ,  Kwang-Soo Kim ,  Sean Park ,  Mitsunori Numata

    IPC: G01N21/00 ,  G01N21/88 ,  G02B27/42 ,  G06T7/00 ,  G01N21/956

    Abstract: An imaging apparatus includes an illumination light source to output an illumination light, an illumination optical system to transmit the illumination light toward a sample, an imaging optical system to transmit light reflected from the sample, a stage to move the sample in a predetermined transfer direction, and a photographing unit to receive the reflected light. The imaging apparatus may include one or more diffraction grids located at conjugate focal planes of the sample. The operation of the photographing unit may be synchronized with a movement of the sample by the stage to obtain an image in accordance with a time delay integration method.

    Vertical semiconductor devices
    8.
    发明授权
    Vertical semiconductor devices 有权

    公开(公告)号：US10224341B2

    公开(公告)日：2019-03-05

    申请号：US15636729

    申请日：2017-06-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kwang-Soo Kim ,  Tae-Seok Jang

    IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573

    Abstract: A vertical semiconductor device includes odd and even cell blocks, and odd and even block pad structures. Each of the odd cell blocks includes first conductive line structures including conductive lines and insulation layers alternatively stacked in a first direction. Each of the even cell blocks includes second conductive line structures having substantially the same shape as the first conductive line structures. The odd block pad structure is connected to first edge portions of the first conductive line structures. The even block pad structure is connected to second edge portions, opposite the first edge portions, of the second conductive line structures. Each of the odd cell blocks and the even cell blocks has a first width in a third direction. Each of the odd and even block pad structures is formed on a region of a substrate having a second width greater than the first width in the third direction.

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