公开(公告)号：US20190238141A1

公开(公告)日：2019-08-01

申请号：US16376444

申请日：2019-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juho Jeon ,  Hun-Dae Choi

IPC: H03L7/081 ,  H03L7/22 ,  H03L7/197 ,  H03L7/087 ,  G11C7/10 ,  G11C29/02 ,  H03L7/10 ,  G11C7/22

CPC classification number: H03L7/0814 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  H03L7/0812 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/10 ,  H03L7/197 ,  H03L7/22

Abstract: A delay locked loop according to some example embodiments of the inventive concepts may include first, second, and third delay circuits, first and second phase detectors, and first and second controllers. The first delay circuit may generate a first clock by delaying a reference clock. The second and third delay circuits may be configured to generate a second and third clock respectively by delaying the first clock. The first and second phase detector may be configured to detect a phase difference between the second clock and the third clock and the third clock respectively. The first controller may be configured to adjust a delay of the third delay circuit using a detection result of the first phase detector. The second controller may be configured to adjust a delay of the first delay circuit using a detection result of the second phase detector.

公开(公告)号：US10141931B2

公开(公告)日：2018-11-27

申请号：US15689855

申请日：2017-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hun-Dae Choi

IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00 ,  H03K3/011

Abstract: A memory device includes a main driver and a pre-driver. The main driver provides an output signal to a host based on a plurality of driving signals. The pre-driver provides the main driver with the plurality of driving signals in order to calibrate a slew rate of the output signal based on an output resistance value of the main driver and a resistance value of an on-die termination circuit of the host. The pre-driver is configured to generate a first driving signal of the plurality of driving signals in response to an input signal regardless of a control signal, and to generate a second driving signal of the plurality of driving signals in response to the input signal and the control signal.

公开(公告)号：US09830972B2

公开(公告)日：2017-11-28

申请号：US14969113

申请日：2015-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk Yong Kang ,  Han-Gi Jung ,  Hun-Dae Choi

IPC: G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4093 ,  G11C7/1084 ,  G11C7/1093

Abstract: Provided is a semiconductor device comprising a signal generator that generates a differential data strobe signal, and a converter that extends a length of a postamble section of the differential data strobe signal from a first length to a second length, wherein the differential data strobe signal enters a high impedance state after the postamble section.

公开(公告)号：US09088287B2

公开(公告)日：2015-07-21

申请号：US14193595

申请日：2014-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hun-Dae Choi ,  In-Dal Song

IPC: H03K23/42 ,  H03K23/66

CPC classification number: H03K23/42 ,  H03K23/667

Abstract: A clock generation device includes a flip-flop, a clock division unit, and a clock comparator. The flip-flop generates a chip selection signal synchronized with an internal clock signal. The clock division unit generates second divided clock signals based on a first divided clock signal. The clock comparator selects ones of the second divided clock signals based on the chip selection signal. The clock division unit divides the internal clock signal based on the first divided clock signal and the selected one of the second divided clock signals.

Abstract translation: 时钟生成装置包括触发器，时钟分割单元和时钟比较器。 触发器产生与内部时钟信号同步的芯片选择信号。 时钟分割单元基于第一分频时钟信号产生第二分频时钟信号。 时钟比较器基于芯片选择信号选择第二分频时钟信号中的一个。 时钟分频单元根据第一分频时钟信号和所选择的第二分频时钟信号中的一个分频内部时钟信号。